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AD6315LF PDF预览

AD6315LF

更新时间: 2024-02-17 06:04:59
品牌 Logo 应用领域
易亨 - ANACHIP 显示驱动器驱动程序和接口控制器
页数 文件大小 规格书
16页 243K
描述
1/4- to 1/12 Duty VFD Controller/Driver

AD6315LF 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:QFP,针数:44
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
Is Samacsys:N数据输入模式:SERIAL
显示模式:DOT MATRIX接口集成电路类型:VACUUM FLUORESCENT DISPLAY DRIVER
JESD-30 代码:S-PQFP-G44长度:10 mm
复用显示功能:YES标称负供电电压:-30 V
位数/字符:12-DIGIT功能数量:1
区段数:28端子数量:44
最高工作温度:70 °C最低工作温度:-20 °C
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:SQUARE封装形式:FLATPACK
认证状态:Not Qualified座面最大高度:2.7 mm
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
宽度:10 mmBase Number Matches:1

AD6315LF 数据手册

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AD6315  
1/4- to 1/12 Duty VFD Controller/Driver  
Pin Descriptions  
Symbol  
Name  
No.  
Description  
Input serial data at rising edge of shift clock,  
DIN  
Data input  
7
starting from the low order bit.  
Output serial data at the falling edge of the  
shift clock, starting from low order bit. This is  
N-ch open-drain output pin.  
DOUT  
STB  
Data output  
Strobe  
6
Initializes serial interface at the rising or  
falling edge of the AD6315. It then waits for  
reception of a command. Data input after  
STB falling is processed as a command.  
While command data is processed, current  
processing is stopped, and the serial  
interface is initialized. While STB is high, CLK  
is ignored.  
9
Reads serial data at the rising edge, and  
outputs data at the falling edge.  
CLK  
Clock input  
8
5
Connect resistor in between this pin and Vss to set  
up the oscillation frequency.  
OSC  
Oscillator pin  
Seg1/KS1 to  
Segment output pins (Dual function as key  
High-voltage output (Segment) 14 to 29  
Seg16/KS16  
source)  
Grid1 to Grid4  
High-voltage output (Grid)  
39 to 42 Grid output pins  
Seg17/Grid12 to  
High-voltage output  
These pins are selectable for segment or grid  
31 to 38  
Seg24/Grid5  
(Segment/grid)  
driving.  
LED1 to LED4  
KEY1, KEY2  
LED output  
1 to 4 CMOS output  
Data input to these pins is latched at the end  
Key data input  
10, 11  
13, 43  
of the display cycle.  
Logic power supply  
VDD  
VSS  
VEE  
Logic power  
Logic ground  
Pull-down level  
12, 44 Connect this pin to system GND.  
Driver power supply  
30  
Ordering Information  
AD6315X X X  
Packing  
Package  
Q: QFP-44L  
Lead  
Blank: Normal  
Blank : Tray  
L : LQFP-44L  
F: Lead Free  
Anachip Corp.  
www.anachip.com.tw  
Rev. A5 Dec 29, 2003  
2/16  

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