AD6312
1/4- to 1/11 Duty VFD Controller/Driver
ꢀPin Descriptions
Symbol
Name
No.
Description
Input serial data at rising edge of shift clock,
DIN
Data input
6
starting from the low order bit.
Output serial data at the falling edge of the shift
clock, starting from low order bit. This is N-ch
open-drain output pin.
DOUT
Data output
5
Initializes serial interface at the rising or falling
edge of the AD6312. It then waits for reception of
a command. Data input after STB falling is
processed as a command. While command data
is processed, current processing is stopped, and
the serial interface is initialized. While STB is
high, CLK is ignored.
STB
CLK
Strobe
9
8
Reads serial data at the rising edge, and outputs
Clock input
data at the falling edge.
Connect resistor in between this pin and Vss to
set up the oscillation frequency.
OSC
Oscillator pin
High-voltage output (Segment)
High-voltage output
44
Seg7 to Seg11
21 to 25
15 to 20
32 to 37
Segment output pins
Seg1/KS1 to
Seg6/KS6
Multi-function pins, Segment output pins (Dual
function as key scan source)
Grid1 to Grid6
High-voltage output (Grid)
High-voltage output (Segment/grid)
LED output
Grid output pins
Seg12/Grid11 to
Seg16/Grid7
26,
These pins are selectable for segment or grid
driving.
28 to 31
LED1 to LED4
39to 42
CMOS output
Data input to these pins is latched at the end of
the display cycle.
KEY1 to KEY4
Key data input
10 to 13
VDD
VSS
Logic power
Logic ground
Pull-down level
Switch input
14, 38
7, 43
27
Logic power supply
Connect this pin to system GND.
Driver power supply
VEE
These pins constitute a 4-bit general-purpose
input port.
SW1 to SW4
1 to 4
ꢀ Ordering Information
AD6312 X X X
Packing
Package
Lead
Q: QFP-44L
L: LQFP-44L
Blank: Normal
F: Lead Free
Blank : Tray
Anachip Corp.
www.anachip.com.tw
Rev. A4 Dec 29, 2003
2/13