AD630
SWITCHED INPUT IMPEDANCE
because the open collector channel status output inverts the
output sense of the internal comparator.
The noninverting mode of operation is a high input impedance
configuration while the inverting mode is a low input impedance
configuration. This means that the input impedance of the
circuit undergoes an abrupt change as the gain is switched un-
der control of the comparator. If gain is switched when the
input signal is not zero, as it is in many practical cases, a tran-
sient will be delivered to the circuitry driving the AD630. In
most applications, this will require the AD630 circuit to be
driven by a low impedance source which remains “stiff “ at high
frequencies. Generally this will be a wideband buffer amplifier.
+5V
100k⍀
1M⍀
100k⍀
9
7
10
8
–15V
100⍀
FREQUENCY COMPENSATION
Figure 16. Comparator Hysteresis
The AD630 combines the convenience of internal frequency
compensation with the flexibility of external compensation by
means of an optional self-contained compensation capacitor.
The channel status output may be interfaced with TTL inputs
as shown in Figure 17. This circuit provides appropriate level
shifting from the open-collector AD630 channel status output to
TTL inputs.
In gain of 2 applications the noise gain which must be addressed
for stability purposes is actually 4. In this circumstance, the
phase margin of the loop will be on the order of 60° without the
optional compensation. This condition provides the maximum
bandwidth and slew-rate for closed-loop gains of |2| and above.
+5V
+15V
100k⍀
22k⍀
6.8k⍀
When the AD630 is used as a multiplexer, or in other configura-
tions where one or both inputs are connected for unity gain
feedback, the phase margin will be reduced to less than 20°.
This may be acceptable in applications where fast slewing is a
first priority, but the transient response will not be optimum.
For these applications, the self-contained compensation capaci-
tor may be added by connecting Pin 12 to Pin 13. This connec-
tion reduces the closed loop bandwidth somewhat, and improves
the phase margin.
IN914's
AD630
7
TTL INPUT
2N2222
8
–15V
Figure 17. Channel Status—TTL Interface
APPLICATIONS: BALANCED MODULATOR
Perhaps the most commonly used configuration of the AD630 is
the balanced modulator. The application resistors provide pre-
cise symmetric gains of 1 and 2. The 1 arrangement is
shown in Figure 18a and the 2 arrangement is shown in Figure
18b. These cases differ only in the connection of the 10k feed-
back resistor (Pin 14) and the compensation capacitor (Pin 12).
Note the use of the 2.5 kΩ bias current compensation resistors
in these examples. These resistors perform the identical function
in the 1 gain case. Figure 19 demonstrates the performance of
the AD630 when used to modulate a 100 kHz square wave
carrier with a 10 kHz sinusoid. The result is the double side-
band suppressed carrier waveform.
For intermediate conditions, such as gain of 1 where loop
attenuation is 2, use of the compensation should be determined
by whether bandwidth or settling response must be optimized.
The optional compensation should also be used when the AD630
is driving capacitive loads or whenever conservative frequency
compensation is desired.
OFFSET VOLTAGE NULLING
The offset voltages of both input stages and the comparator
have been pretrimmed so that external trimming will only be
required in the most demanding applications. The offset adjust-
ment of the two input channels is accomplished by means of a
differential and common-mode scheme. This facilitates fine
adjustment of system errors in switched gain applications. With
system input tied to 0 V, and a switching or carrier waveform
applied to the comparator, a low level square wave will appear at
the output. The differential offset adjustment pot can be used
to null the amplitude of this square wave (Pins 3 and 4). The
common-mode offset adjustment can be used to zero the re-
sidual dc output voltage (Pins 5 and 6). These functions should
be implemented using 10k trim pots with wipers connected
directly to Pin 8 as shown in Figures 18a and 18b.
These balanced modulator topologies accept two inputs, a signal
(or modulation) input applied to the amplifying channels, and a
reference (or carrier) input applied to the comparator.
10k⍀
10k⍀
DIFF
ADJ
CM
ADJ
6
4
3
5
2.5k⍀
2.5k⍀
MODULATION
INPUT
1
2
AMP A
12
11
13
A
+V
S
20
B
CHANNEL STATUS OUTPUT
10k⍀
MODULATED
OUTPUT
SIGNAL
17
18
AMP B
14
15
16
The channel status output, Pin 7, is an open collector output
referenced to –VS which can be used to indicate which of the
two input channels is active. The output will be active (pulled
low) when Channel A is selected. This output can also be used
to supply positive feedback around the comparator. This pro-
duces hysteresis which serves to increase noise immunity. Figure
16 shows an example of how hysteresis may be implemented.
Note that the feedback signal is applied to the inverting (–)
terminal of the comparator to achieve positive feedback. This is
–V
10k⍀
19
AD630
CARRIER
INPUT
5k⍀
COMP
7
9
10
8
–V
S
Figure 18a. AD630 Configured as a Gain-of-One Balanced
Modulator
–6–
REV. C
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