AD585SE

更新时间： 2024-01-26 08:21:34

品牌	Logo	应用领域
亚德诺 - ADI		采样保持电路放大器放大器电路
页数	文件大小	规格书
6页	342K
描述
High Speed, Precision Sample-and-Hold Amplifier

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技术参数
数据手册

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AD585SE 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QLCC
包装说明：	QCCN, LCC20,.35SQ	针数：	20
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.31.00.01	风险等级：	7.7
Is Samacsys：	N	最长采集时间：	5 µs
放大器类型：	SAMPLE AND HOLD CIRCUIT	最大模拟输入电压：	18 V
最小模拟输入电压：	-18 V	最大下降率：	1 V/s
JESD-30 代码：	S-CQCC-N20	JESD-609代码：	e4
长度：	8.89 mm	负供电电压上限：	-18 V
标称负供电电压 (Vsup)：	-15 V	功能数量：	1
端子数量：	20	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	QCCN	封装等效代码：	LCC20,.35SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	NOT APPLICABLE	电源：	+-12/+-15 V
认证状态：	Not Qualified	采样并保持/跟踪并保持：	SAMPLE
座面最大高度：	2.54 mm	子类别：	Sample and Hold Circuit
最大压摆率：	10 mA	供电电压上限：	18 V
标称供电电压 (Vsup)：	15 V	表面贴装：	YES
温度等级：	MILITARY	端子面层：	Gold (Au)
端子形式：	NO LEAD	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT APPLICABLE
宽度：	8.89 mm	Base Number Matches：	1

AD585SE 数据手册

AD585

SAMPLED DATA SYSTEMS

2^{–(N +1)}

In sampled data systems there are a number of limiting factors

in digitizing high frequency signals accurately. Figure 9 shows

pictorially the sample-and-hold errors that are the limiting fac-

tors. In the following discussions of error sources the errors will

be divided into the following groups: 1. Sample-to-Hold Transi-

tion, 2. Hold Mode and 3. Hold-to-Sample Transition.

f_MAX

π (Aperture Jitter)

For an application with a 10-bit A/D converter with a 10 V full

scale to a 1/2 LSB error maximum.

2^{–(10 +1)}

π (0.5 × 10^–9

f_MAX

)

f_MAX= 310.8 kHz.

For an application with a 12-bit A/D converter with a 10 V full

scale to a 1/2 LSB error maximum:

2^{–(12 +1)}

π (0.5 × 10^–9

f_MAX

)

f_MAX= 77.7 kHz.

Figure 11 shows the entire range of errors induced by aperture

jitter with respect to the input signal frequency.

Figure 9. Pictorial Showing Various S/H Characteristics

SAMPLE-TO-HOLD TRANSITION

The aperture delay time is the time required for the sample-and-

hold amplifier to switch from sample to hold. Since this is effec-

tively a constant then it may be tuned out. If however, the

aperture delay time is not accounted for then errors of the mag-

nitude as shown in Figure 10 will result.

Figure 11. Aperture Jitter Error vs. Frequency

Sample-to-hold offset is caused by the transfer of charge to the

holding capacitor via the gate capacitance of the switch when

switching into hold. Since the gate capacitance couples the

switch control voltage applied to the gate on to the hold capaci-

tor, the resulting sample-to-hold offset is a function of the logic

level .

Figure 10. Aperture Delay Error vs. Frequency

The logic inputs were designed for application flexibility and,

therefore, a wide range of logic thresholds. This was achieved by

using a differential input stage for HOLD and HOLD. Figure 1

shows the change in the sample-to-hold offset voltage based

upon an independently programmed reference voltage. Since

the input stage is a differential configuration, the offset voltage

is a function of the control voltage range around the pro-

grammed threshold voltage.

To eliminate the aperture delay as an error source the sample-

to-hold command may be advanced with respect to the input

signal .

Once the aperture delay time has been eliminated as an error

source then the aperture jitter which is the variation in aperture

delay time from sample-to-sample remains. The aperture jitter is

a true error source and must be considered. The aperture jitter

is a result of noise within the switching network which modu-

lates the phase of the hold command and is manifested in the

variations in the value of the analog input that has been held.

The aperture error which results from this jitter is directly re-

lated to the dV/dT of the analog input.

The sample-to-hold offset can be reduced by adding capacitance

to the internal 100 pF capacitor and by using HOLD instead of

HOLD. This may be easily accomplished by adding an external

capacitor between Pins 7 and 8. The sample-to-hold offset is

then governed by the relationship:

The error due to aperture jitter is easily calculated as shown be-

low. The error calculation takes into account the desired accu-

racy corresponding to the resolution of the N-bit A/D converter.

Charge pC

C_HTotal (pF )

(

)

S/H Offset (V ) =

–4–

REV. A

1 2 345 6

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AD585SE/883B	ETC	Sample/Track-and-Hold Amplifier	获取价格
AD585SQ	ADI	High Speed, Precision Sample-and-Hold Amplifier	获取价格
AD585SQ	ROCHESTER	暂无描述	获取价格
AD585SQ/883B	ETC	Sample/Track-and-Hold Amplifier	获取价格
AD586	ADI	High Precision 5 V Reference	获取价格
AD586_05	ADI	High Precision 5 V Reference	获取价格

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