Datasheet > AD5752AREZ-REEL7

AD5752AREZ-REEL7

更新时间： 2022-12-21 14:11:49

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
32页	990K
描述
Complete, Dual, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DACs

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AD5752AREZ-REEL7 数据手册

AD5722/AD5732/AD5752

AC PERFORMANCE CHARACTERISTICS

AV_DD= 4.5 V¹to 16.5 V; AV_SS= −4.5 V to −16.5 V, or AV_SS= 0 V; GND = 0 V; REFIN = 2.5 V; DV_CC= 2.7 V to 5.5 V; R_LOAD= 2 kΩ;

_LOAD= 200 pF; all specifications T_MINto T_MAX, unless otherwise noted.

Table 2.

Parameter²

Min

Typ

Max

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time

7.5

8.5

μs

20 V step to 0.03% FSR

10 V step to 0.03% FSR

512 LSB step settling (16-bit resolution)

Slew Rate

3.5

0.6

V/μs

nV-sec

Digital-to-Analog Glitch Energy

Glitch Impulse Peak Amplitude

Digital Crosstalk

DAC-to-DAC Crosstalk

Digital Feedthrough

Output Noise

0.1 Hz to 10 Hz Bandwidth

100 kHz Bandwidth

Output Noise Spectral Density

320

μV p-p

μV rms

nV/√Hz

0x8000 DAC code

Measured at 10 kHz, 0x8000 DAC code

¹For specified performance, the maximum headroom requirement is 0.9 V.

²Guaranteed by design and characterization; not production tested.

TIMING CHARACTERISTICS

AV_DD= 4.5 V to 16.5 V; AV_SS= −4.5 V to −16.5 V, or AV_SS= 0 V; GND = 0 V; REFIN = 2.5 V; DV_CC= 2.7 V to 5.5 V; R_LOAD= 2 kΩ; C_LOAD

200 pF; all specifications t_MINto t_MAX, unless otherwise noted.

Table 3.

Parameter^{1, 2, 3}

Limit at t_MIN, t_MAX

Unit

Description

t₁

t₂

t₃

t₄

100

ns min

μs max

ns min

μs max

ns min

ns max

ns min

SCLK cycle time

SCLK high time

SCLK low time

SYNC falling edge to SCLK falling edge setup time

SCLK falling edge to SYNC rising edge

Minimum SYNC high time (write mode)

Data setup time

t₅

t₆

t₇

t₈

t₉

Data hold time

2.5

200

LDAC falling edge to SYNC falling edge

SYNC rising edge to LDAC falling edge

LDAC pulse width low

t₁₀

t₁₁

t₁₂

t₁₃

t₁₄

DAC output settling time

CLR pulse width low

CLR pulse activation time

t₁₅

SYNC rising edge to SCLK falling edge

SCLK rising edge to SDO valid (C_{L SDO}⁵= 15 pF)

Minimum SYNC high time (readback/daisy-chain mode)

t₁₆

t₁₇

¹Guaranteed by characterization; not production tested.

²All input signals are specified with t_R= t_F= 5 ns (10% to 90% of DV_CC) and timed from a voltage level of 1.2 V.

³See Figure 2, Figure 3, and Figure 4.

⁴Daisy-chain and readback mode.

⁵C_{L SDO}= capacitive load on SDO output.

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