AD548
Figure 22. Board Layout for Guarding Inputs
Figure 24. AD548 Used as DAC Output Am plifier
T hat is:
INP UT P RO TECTIO N
T he AD548 is guaranteed to withstand input voltages equal to
the power supply potential. Exceeding the negative supply volt-
age on either input will forward bias the substrate junction of
the chip. T he induced current may destroy the amplifier due to
excess heat.
RFB
RO
VOS Output =VOS Input 1+
RFB is the feedback resistor for the op amp, which is internal to
the DAC. RO is the DAC’s R-2R ladder output resistance. T he
value of RO is code dependent. T his has the effect of changing
the offset error voltage at the amplifier’s output. An output am-
plifier with a sub millivolt input offset voltage is needed to
preserve the linearity of the DAC’s transfer function.
Input protection is required in applications such as a flame
detector in a gas chromatograph, where a very high potential
may be applied to the input terminals during a sensor fault con-
dition. Figure 23 shows a simple current limiting scheme that
can be used. RPROT ECT should be chosen such that the maxi-
mum overload current is 1.0 mA (l00 kΩ for a 100 V overload,
for example).
T he AD548 in this configuration provides a 700 kHz small sig-
nal bandwidth and 1.8 V/µs typical slew rate. T he 33 pF capaci-
tor across the feedback resistor optimizes the circuit’s response.
T he oscilloscope photos in Figures 25 and 26 show small and
large signal outputs of the circuit in Figure 24. Upper traces
show the input signal VIN. Lower traces are the resulting output
voltage with the DAC’s digital input set to all 1s. T he AD548
settles to ±0.01% for a 20 V input step in 14 µs.
Exceeding the negative common-mode range on either input
terminal causes a phase reversal at the output, forcing the
amplifier output to the corresponding high or low state. Exceed-
ing the negative common-mode on both inputs simultaneously
forces the output high. Exceeding the positive common-mode
range on a single input doesn’t cause a phase reversal, but if
both inputs exceed the limit the output will be forced high. In
all cases, normal amplifier operation is resumed when input
voltages are brought back within the common-mode range.
5V
20V
5µS
100
90
10
0%
Figure 25. Response to ±20 V p-p Reference Square Wave
50mV
200mV
2µS
Figure 23. Input Protection of IV Converter
100
90
D /A CO NVERTER O UTP UT BUFFER
T he circuit in Figure 24 shows the AD548 and AD7545 12-bit
CMOS D/A converter in a unipolar binary configuration. VOUT
will be equal to VREF attenuated by a factor depending on the
digital word. VREF sets the full scale. Overall gain is trimmed by
adjusting RIN. T he AD548’s low input offset voltage, low drift
and clean dynamics make it an attractive low power output
buffer.
10
0%
Figure 26. Response to ±100 m V p-p Reference Square
Wave
T he input offset voltage of the AD548 output amplifier results
in an output error voltage. T his error voltage equals the input
offset voltage of the op amp times the noise gain of the
amplifier.
–6–
REV. C