AD536AJQ

更新时间： 2024-02-29 01:27:46

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
8页	152K
描述
Integrated Circuit True RMS-to-DC Converter

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AD536AJQ 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	not_compliant	风险等级：	5.92
转换器类型：	RMS TO DC CONVERTER	JESD-30 代码：	R-XDIP-T14
JESD-609代码：	e0	端子数量：	14
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC	封装代码：	DIP
封装等效代码：	DIP14,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	电源：	5/36/+-3/+-18 V
子类别：	Analog Special Function Converters	最大压摆率：	2 mA
表面贴装：	NO	技术：	BIPOLAR
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	Base Number Matches：	1

AD536AJQ 数据手册

AD536A

The two-pole post-filter uses an active filter stage to provide

even greater ripple reduction without substantially increasing

the settling times over a circuit with a one-pole filter. The values

of C_AV, C2, and C3 can then be reduced to allow extremely fast

settling times for a constant amount of ripple. Caution should

be exercised in choosing the value of C_AV, since the dc error is

dependent upon this value and is independent of the post filter.

factors, (such as low duty cycle pulse trains), the averaging time

constant should be at least ten times the signal period. For

example, a 100 Hz pulse rate requires a 100 ms time constant,

which corresponds to a 4 µF capacitor (time constant = 25 ms

per µF).

The primary disadvantage in using a large C_AVto remove ripple

is that the settling time for a step change in input level is in-

creased proportionately. Figure 5 shows that the relationship

between C_AVand 1% settling time is 115 milliseconds for each

microfarad of C_AV. The settling time is twice as great for de-

creasing signals as for increasing signals (the values in Figure 5

are for decreasing signals). Settling time also increases for low

signal levels, as shown in Figure 6.

For a more detailed explanation of these topics refer to the

RMS to DC Conversion Application Guide 2nd Edition, available

from Analog Devices.

Figure 7. 2-Pole “Post” Filter

Figure 5. Error/Settling Time Graph for Use with the Stan-

dard rms Connection in Figure 1

Figure 6. Settling Time vs. Input Level

Figure 8. Performance Features of Various Filter Types

A better method for reducing output ripple is the use of a

“post-filter.” Figure 7 shows a suggested circuit. If a single-pole

filter is used (C3 removed, R_Xshorted), and C2 is approximately

twice the value of C_AV, the ripple is reduced as shown in Figure

8 and settling time is increased. For example, with C_AV= 1 µF

and C2 = 2.2 µF, the ripple for a 60 Hz input is reduced from

10% of reading to approximately 0.3% of reading. The settling

time, however, is increased by approximately a factor of 3. The

values of C_AVand C2_,can, therefore, be reduced to permit faster

settling times while still providing substantial ripple reduction.

AD536A PRINCIPLE OF OPERATION

The AD536A embodies an implicit solution of the rms equation

that overcomes the dynamic range as well as other limitations

inherent in a straightforward computation of rms. The actual

computation performed by the AD536A follows the equation:











V_IN

V rms = Avg.

V rms 



REV. B

–5–

1 2 3 456 7 8

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与AD536AJQ相关器件

型号	品牌	描述	获取价格	数据表
AD536AKCD	ETC	RMS-to-DC Converter	获取价格
AD536AKCQ	ETC	RMS-to-DC Converter	获取价格
AD536AKCWE	ETC	RMS-to-DC Converter	获取价格
AD536AKD	ADI	Integrated Circuit True RMS-to-DC Converter	获取价格
AD536AKD	MAXIM	RMS to DC Converter, Bipolar, CDIP14,	获取价格
AD536AKD/+	ETC	RMS-to-DC Converter	获取价格

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