AD5348BRU-REEL

更新时间： 2024-01-11 01:12:41

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	944K
描述
2.5 V to 5.5 V, Parallel Interface 2.5 V to 5.5 V, Parallel Interface

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AD5348BRU-REEL 数据手册

AD5346/AD5347/AD5348

B Version¹

Typ

Parameter²

Min

Max

0.4

Unit

Conditions/Comments

LOGIC OUTPUTS⁶

V_DD= 4.5 V to 5.5 V

Output Low Voltage, V_OL

Output High Voltage, V_OH

V_DD= 2.5 V to 3.6 V

Output Low Voltage, V_OL

Output High Voltage, V_OH

POWER REQUIREMENTS

V_DD

I_SINK= 200 µA

I_SOURCE= 200 µA

V_DD– 1

0.4

I_SINK= 200 µA

I_SOURCE= 200 µA

V_DD– 0.5

2.5

5.5

I_DD(Normal Mode)

V_DD= 4.5 V to 5.5 V

V_DD= 2.5 V to 3.6 V

V_IH= V_DD, V_IL= GND

All DACs in unbuffered mode. In buffered mode,

extra current is typically x µA per DAC, where x = 5 µA +

V_REF/R_DAC

0.8

1.65

1.4

I_DD(Power-Down Mode)

V_DD= 4.5 V to 5.5 V

V_DD= 2.5 V to 3.6 V

V_IH= V_DD, V_IL= GND

0.4

0.12

µA

See footnotes after the AC Characteristics table.

AC CHARACTERISTICS⁶

Table 2. V_DD= 2.5 V to 5.5 V; R_L= 2 kΩ to GND; C_L= 200 pF to GND; all specifications T_MINto T_MAX, unless otherwise noted

B Version¹

Min Typ

Parameter²

Output Voltage Settling Time

AD5346

Max

Unit

Conditions/Comments

V_REF= 2 V

µs

1/4 scale to 3/4 scale change (40 H to C0 H)

1/4 scale to 3/4 scale change (100 H to 300 H)

1/4 scale to 3/4 scale change (400 H to C00 H)

AD5347

AD5348

Slew Rate

0.7

V/µs

Major Code Transition Glitch

Energy

nV-s

1 LSB change around major carry

Digital Feedthrough

Digital Crosstalk

Analog Crosstalk

DAC-to-DAC Crosstalk

Multiplying Bandwidth

Total Harmonic Distortion

0.5

3.5

200

–70

nV-s

kHz

V_REF= 2 V 0.1 V p-p; unbuffered mode

V_REF= 2. V 0.1 V p-p; frequency = 10 kHz; unbuffered mode

¹Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.

²See Terminology section.

³Linearity is tested using a reduced code range: AD5346 (Code 8 to 255); AD5347 (Code 28 to 1023); AD5348 (Code 115 to 4095).

⁴DC specifications tested with outputs unloaded.

⁵This corresponds to x codes. x = deadband voltage/LSB size.

⁶Guaranteed by design and characterization, not production tested.

⁷For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, V_REF= V_DDand

the offset plus gain error must be positive.

200µA

TO OUTPUT

(min) + V (max)

50pF

200µA

Figure 2. Load Circuit for Digital Output Timing Specifications

Rev. 0 | Page 4 of 24

1 2 345 6 7...24

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