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AD5338BRMZ-1REEL7 PDF预览

AD5338BRMZ-1REEL7

更新时间: 2024-01-28 16:06:51
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 928K
描述
2.5 V to 5.5 V, 250 UA, 2-Wire Interface Dual-Voltage Output, 8-/10-/12-Bit DACs

AD5338BRMZ-1REEL7 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP8,.19针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.26
最大模拟输出电压:5.499 V最小模拟输出电压:0.001 V
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:SERIALJESD-30 代码:S-PDSO-G8
JESD-609代码:e3长度:3 mm
最大线性误差 (EL):0.1953%湿度敏感等级:1
位数:10功能数量:1
端子数量:8最高工作温度:105 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP8,.19
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3/5 V
认证状态:Not Qualified座面最大高度:1.1 mm
最大稳定时间:9 µs标称安定时间 (tstl):7 µs
子类别:Other Converters最大压摆率:0.375 mA
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
Base Number Matches:1

AD5338BRMZ-1REEL7 数据手册

 浏览型号AD5338BRMZ-1REEL7的Datasheet PDF文件第3页浏览型号AD5338BRMZ-1REEL7的Datasheet PDF文件第4页浏览型号AD5338BRMZ-1REEL7的Datasheet PDF文件第5页浏览型号AD5338BRMZ-1REEL7的Datasheet PDF文件第7页浏览型号AD5338BRMZ-1REEL7的Datasheet PDF文件第8页浏览型号AD5338BRMZ-1REEL7的Datasheet PDF文件第9页 
AD5337/AD5338/AD5339  
TIMING CHARACTERISTICS  
VDD = 2.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.  
Table 3.  
Limit at TMIN, TMAX  
Parameter  
(A and B Versions)  
4±±  
2.5  
±.ꢀ  
1.3  
±.ꢀ  
1±±  
±.9  
±
±.ꢀ  
±.ꢀ  
1.3  
3±±  
±
25±  
±
Unit  
Conditions/Comments  
fSCL  
t1  
t2  
t3  
t4  
kHz max  
µs min  
µs min  
µs min  
µs min  
ns min  
µs max  
µs min  
µs min  
µs min  
µs min  
ns max  
ns min  
ns max  
ns min  
ns max  
ns min  
pF max  
SCL clock frequency  
SCL cycle time  
tHIGH, SCL high time  
tLOW, SCL low time  
tHD, STA, start/repeated start condition hold time  
tSU, DAT, data setup time  
tHD, DAT, data hold time  
t5  
tꢀ  
1
tHD, DAT, data hold time  
t7  
t8  
t9  
t1±  
tSU, STA, setup time for repeated start  
tSU, STO, stop condition setup time  
tBUF, bus free time between a stop and a start condition  
tR, rise time of SCL and SDA when receiving  
tR, rise time of SCL and SDA when receiving (CMOS-compatible)  
tF, fall time of SDA when transmitting  
tF, fall time of SDA when receiving (CMOS-compatible)  
tF, fall time of SCL and SDA when receiving  
tF, fall time of SCL and SDA when transmitting  
Capacitive load for each bus line  
t11  
3±±  
2± + ±.1 CB  
4±±  
2
CB  
1 A master device must provide a hold time of at least 3±± ns for the SDA signal (referred to VIH min of the SCL signal) in order to bridge the undefined region of SCL’s  
falling edge.  
2 CB is the total capacitance of one bus line in pF; tR and tF measured between ±.3 VDD and ±.7 VDD  
.
SDA  
t9  
t3  
t10  
t11  
t4  
SCL  
t4  
t2  
t6  
t1  
t8  
t5  
t7  
START  
CONDITION  
REPEATED  
START  
STOP  
CONDITION  
CONDITION  
Figure 2. 2-Wire Serial Interface Timing Diagram  
Rev. A | Page ꢀ of 24  
 
 
 
 

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