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AD5330BRUZ1 PDF预览

AD5330BRUZ1

更新时间: 2024-02-01 15:35:57
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 542K
描述
2.5 V to 5.5 V, 115 μA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs

AD5330BRUZ1 数据手册

 浏览型号AD5330BRUZ1的Datasheet PDF文件第1页浏览型号AD5330BRUZ1的Datasheet PDF文件第2页浏览型号AD5330BRUZ1的Datasheet PDF文件第3页浏览型号AD5330BRUZ1的Datasheet PDF文件第5页浏览型号AD5330BRUZ1的Datasheet PDF文件第6页浏览型号AD5330BRUZ1的Datasheet PDF文件第7页 
AD5330/AD5331/AD5340/AD5341  
B Version2  
Min Typ  
Parameter1  
Max  
Unit  
Conditions/Comments  
POWER REQUIREMENTS  
VDD  
2.5  
5.5  
V
IDD (Normal Mode)  
VDD = 4.5 V to 5.5 V  
VDD = 2.5 V to 3.1 V  
DACs active and excluding load currents. Unbuffered  
Reference, VIH = VDD, VIL = GND  
IDD increases by 50 μA at VREF > VDD − ꢀ00 mV.  
ꢀ40  
ꢀꢀ5  
250  
200  
μA  
μA  
In buffered mode, extra current is (5 + VREF/RDAC) μA,  
where RDAC is the resistance of the resistor string.  
IDD (Power-Down Mode)  
VDD = 4.5 V to 5.5 V  
VDD = 2.5 V to 3.1 V  
0.2  
0.08  
μA  
μA  
See the Terminology section.  
2 Temperature range: B Version: −40°C to +ꢀ05°C; typical specifications are at 25°C.  
3 Linearity is tested using a reduced code range: AD5330 (Code 8 to Code 255); AD533ꢀ (Code 28 to Code ꢀ023); AD5340/AD534ꢀ (Code ꢀꢀ5 to Code 4095).  
4 DC specifications tested with output unloaded.  
5 This corresponds to x codes. x = deadband voltage/LSB size.  
1 Guaranteed by design and characterization, not production tested.  
7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and offset plus  
gain error must be positive.  
AC CHARACTERISTICS1  
VDD = 2.5 V to 5.5 V. RL = 2 kΩ to GND, CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.  
Table 2.  
B Version3  
Min Typ Max  
Parameter2  
Unit  
Conditions/Comments  
Output Voltage Settling Time  
AD5330  
AD533ꢀ  
AD5340  
AD534ꢀ  
VREF = 2 V; see Figure 29  
1
7
8
8
8
9
ꢀ0  
ꢀ0  
μs  
μs  
μs  
μs  
¼ scale to ¾ scale change (0x40 to 0xC0)  
¼ scale to ¾ scale change (0xꢀ00 to 0x300)  
¼ scale to ¾ scale change (0x400 to 0xC00)  
¼ scale to ¾ scale change (0x400 to 0xC00)  
Slew Rate  
0.7  
1
0.5  
200  
−70  
V/μs  
nV/s  
nV/s  
kHz  
dB  
Major Code Transition Glitch Energy  
Digital Feedthrough  
Multiplying Bandwidth  
Total Harmonic Distortion  
ꢀ LSB change around major carry  
VREF = 2 V 0.ꢀ V p-p; unbuffered mode  
VREF = 2.5 V 0.ꢀ V p-p; frequency = ꢀ0 kHz  
Guaranteed by design and characterization, not production tested.  
2 See the Terminology section.  
3 Temperature range: B Version: −40°C to +ꢀ05°C; typical specifications are at 25°C.  
Rev. A | Page 4 of 28  
 
 

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