Datasheet > AD5320BRMZ-REEL1

AD5320BRMZ-REEL1

更新时间： 2022-04-12 00:26:18

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
20页	410K
描述
2.7 V to 5.5 V, 140 Î¼A, Rail-to-Rail Output 12-Bit DAC in an SOT-23

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AD5320BRMZ-REEL1 数据手册

AD5320

TIMING CHARACTERISTICS

V_DD= 2.7 V to 5.5 V, all specifications T_MINto T_MAX, unless otherwise noted.

Table 2.

Limit at T_MIN, T_MAX

Parameter^{1, 2}

V_DD= 2.7 V to 3.6 V

V_DD= 3.6 V to 5.5 V

Unit

Description

t₁

22.5

ns min

SCLK cycle time

SCLK high time

SCLK low time

SYNC to SCLK rising edge setup time

Data setup time

Data hold time

SCLK falling edge to SYNC rising edge

Minimum SYNC high time

t₂

t₃

t₄

t₅

t₆

t₇

t₈

4.5

¹All input signals are specified with tr = tf = 5 ns (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

²See Figure 2.

³Maximum SCLK frequency is 30 MHz at V_DD= 3.6 V to 5.5 V and 20 MHz at V_DD= 2.7 V to 3.6 V.

t₁

SCLK

t₂

t₄

t₃

t₇

t₈

SYNC

DIN

t₆

t₅

DB15

DB0

Figure 2. Serial Write Operation

Rev. C | Page 4 of 20

1 2 345 6 7...20

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