Datasheet > AD5315ARMZ1

AD5315ARMZ1

更新时间： 2022-04-21 15:34:56

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	565K
描述
2.5 V to 5.5 V, 500 Î¼A, 2-Wire Interface Interface

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数据手册

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AD5315ARMZ1 数据手册

AD5305/AD5315/AD5325

A Version¹

Typ

B Version¹

Typ

Parameter²

LOGIC INPUTS (A0)⁵

Input Current

Min

Max

Min

Max

Unit

Conditions/Comments

0.8

0.6

0.5

0.8

0.6

0.5

μA

Input Low Voltage, V_IL

V_DD= 5 V 10%

V_DD= 3 V 10%

V_DD= 2.5 V

Input High Voltage, V_IH

2.4

2.1

2.0

2.4

2.1

2.0

V_DD= 5 V 10%

V_DD= 3 V 10%

V_DD= 2.5 V

Pin Capacitance

LOGIC INPUTS (SCL, SDA)⁵

Input High Voltage, V_IH

0.7

V_DD

−0.3

V_DD

0.3

0.7

V_DD

0.3

0.3 V_DD

SMBus compatible at V_DD< 3.6 V

Input Low Voltage, V_IL

Input Leakage Current, I_IN

Input Hysteresis, V_HYST

0.3 V_DD−0.3

μA

0.05

V_DD

0.05

V_DD

Input Capacitance, C_IN

Glitch Rejection

Input filtering suppresses noise spikes

of less than 50 ns

LOGIC OUTPUT (SDA)⁵

Output Low Voltage, V_OL

0.4

0.6

0.4

0.6

μA

I_SINK= 3 mA

I_SINK= 6 mA

Three-State Leakage Current

Three-State Output

Capacitance

POWER REQUIREMENTS

V_DD

2.5

5.5

2.5

5.5

I_DD(Normal Mode)⁷

V_DD= 4.5 V to 5.5 V

V_DD= 2.5 V to 3.6 V

I_DD(Power-Down Mode)

V_DD= 4.5 V to 5.5 V

V_IH= V_DDand V_IL= GND

I_DD= 4 μA (maximum) during

0 readback on SDA

600

500

900

700

600

500

900

700

μA

0.2

μA

V_DD= 2.5 V to 3.6 V

0.08

I_DD= 1.5 μA (maximum) during

0 readback on SDA

¹Temperature range (A, B version): −40°C to +105°C; typical at +25°C.

²See the Terminology section.

³DC specifications tested with the outputs unloaded.

⁴Linearity is tested using a reduced code range: AD5305 (Code 8 to 248); AD5315 (Code 28 to 995); AD5325 (Code 115 to 3981).

⁵Guaranteed by design and characterization, not production tested.

⁶For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, V_REF= V_DDand offset plus gain error must be

positive.

⁷I_DDspecification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.

Rev. G | Page 4 of 24

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