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AD5280BRU200-REEL7 PDF预览

AD5280BRU200-REEL7

更新时间： 2024-01-05 22:57:08
品牌 Logo 应用领域
亚德诺 - ADI 转换器数字电位计电阻器光电二极管
页数 文件大小 规格书
28页 964K
描述
Single/Dual,15 V/5 V,256-Position I2C-Compatible Digital Potentiometer

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AD5280BRU200-REEL7 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：MO-153AB-1, TSSOP-14
针数：14Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.38其他特性：CAN ALSO OPERATE FROM A SINGLE +5V TO +15V SUPPLY; ALSO REQUIRES A +2.7V TO +5.5V LOGIC SUPPLY
标称带宽：0.035 kHz控制接口：2-WIRE SERIAL
转换器类型：DIGITAL POTENTIOMETERJESD-30 代码：R-PDSO-G14
JESD-609代码：e0长度：5 mm
湿度敏感等级：1标称负供电电压：-5 V
功能数量：1位置数：256
端子数量：14最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP14,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：240电源：5/15/+-5 V
认证状态：Not Qualified电阻定律：LINEAR
最大电阻容差：30%最大电阻器端电压：5 V
最小电阻器端电压：-5 V座面最大高度：1.2 mm
子类别：Digital Potentiometers标称供电电压：5 V
表面贴装：YES标称温度系数：30 ppm/ °C
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
标称总电阻：200000 Ω宽度：4.4 mm
Base Number Matches：1

AD5280BRU200-REEL7 数据手册

 浏览型号AD5280BRU200-REEL7的Datasheet PDF文件第1页浏览型号AD5280BRU200-REEL7的Datasheet PDF文件第2页浏览型号AD5280BRU200-REEL7的Datasheet PDF文件第3页浏览型号AD5280BRU200-REEL7的Datasheet PDF文件第5页浏览型号AD5280BRU200-REEL7的Datasheet PDF文件第6页浏览型号AD5280BRU200-REEL7的Datasheet PDF文件第7页 
AD5ꢀ80/AD5ꢀ8ꢀ  
Parameter  
Symbol  
Conditions  
Min  
Typ1  
Max  
Unit  
Total Harmonic Distortion  
THDW  
VA = 1 V rms, RAB = 20 kΩ  
VB = 0 V dc, f = 1 kHz  
0.01/  
%
VW Settling Time  
Crosstalk  
tS  
VA = 5 V, VB = 5 V, 1 LSB error band  
5
μs  
CT  
VA = VDD, VB = 0 V, measure VW1 with  
adjacent RDAC making full-scale  
code change  
15  
nV-s  
Analog Crosstalk  
CTA  
Measure VW1 with VW2 = 5 V p-p @ f =  
10 kHz  
RWB = 20 kΩ, f = 1 kHz  
−62  
18  
dB  
Resistor Noise Voltage  
eN_WB  
nVꢀ√Hz  
INTERFACE TIMING CHARACTERISTICS (applies to all parts)6, 10, 11  
SCL Clock Frequency  
fSCL  
t1  
/00  
kHz  
μs  
0
1.3  
tBUF Bus Free Time Between  
Stop and Start  
tHD:STA Hold Time (Repeated  
Start)  
t2  
After this period, the first clock pulse 0.6  
is generated  
μs  
tLOW Low Period of SCL Clock  
tHIGH High Period of SCL Clock  
t3  
t/  
t5  
1.3  
0.6  
0.6  
μs  
μs  
μs  
tSU:STA Setup Time for Start  
Condition  
tHD:DAT Data Hold Time  
tSU:DAT Data Setup Time  
t6  
t7  
t8  
0.9  
μs  
ns  
ns  
0
100  
tF Fall Time of Both SDA and  
SCL Signals  
tR Rise Time of Both SDA and  
SCL Signals  
tSU:STO Setup Time for STOP  
Condition  
300  
300  
t9  
ns  
μs  
t10  
0.6  
1 Typicals represent average readings at 25°C, VDD = +5 V, VSS = −5 V.  
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper  
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.  
3 VAB = VDD, wiper (VW) = no connect.  
/ INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits  
of ±1 LSB maximum are guaranteed monotonic operating conditions.  
5 Resistor Terminal A, Resistor Terminal B, and Wiper Terminal W have no limitations on polarity with respect to each other.  
6 Guaranteed by design and not subject to production test.  
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.  
8 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest  
bandwidth. The highest R value results in the minimum overall power consumption.  
9 All dynamic characteristics use VDD = 5 V.  
10 See timing diagram (Figure 3) for location of measured values.  
11 Standard I2C mode operation is guaranteed by design.  
t2  
t8  
t6  
t9  
SCL  
SDA  
t10  
t4  
t7  
t5  
t2  
t3  
t9  
t8  
t1  
P
S
S
P
Figure 3. Detailed Timing Diagram  
Rev. C | Page / of 28  
 
 
 
 
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