Datasheet > AD5273BRJZ50-REEL7

AD5273BRJZ50-REEL7

更新时间： 2024-02-25 13:03:31

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		光电二极管
页数	文件大小	规格书
25页	1621K
描述
50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO8, ROHS COMPLIANT, MO-178BA, SOT-23, 8 PIN

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AD5273BRJZ50-REEL7 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	LSSOP,	针数：	8
Reach Compliance Code：	unknown	风险等级：	5.77
其他特性：	NON VOLATILE MEMORY	标称带宽：	0.11 kHz
控制接口：	2-WIRE SERIAL	转换器类型：	DIGITAL POTENTIOMETER
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e4
长度：	2.9 mm	湿度敏感等级：	1
功能数量：	1	位置数：	64
端子数量：	8	最高工作温度：	105 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
认证状态：	COMMERCIAL	电阻定律：	LINEAR
最大电阻容差：	30%	最大电阻器端电压：	5.5 V
最小电阻器端电压：		座面最大高度：	1.45 mm
标称供电电压：	3 V	表面贴装：	YES
标称温度系数：	300 ppm/ °C	温度等级：	INDUSTRIAL
端子面层：	NICKEL PALLADIUM GOLD	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	标称总电阻：	50000 Ω
宽度：	1.6 mm	Base Number Matches：	1

AD5273BRJZ50-REEL7 数据手册

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AD5273

Parameter

Symbol

P_DISS

PSRR

Test Conditions/Comments

V_IH= 5 V or V_IL= 0 V, V_DD= 5 V

R_AB= 1 kΩ

Min

Typ¹

0.5

Max

27.5

+0.3

+0.05

Unit

μW

%/%

Power Dissipation¹²

Power Supply Sensitivity

−0.3

−0.05

PSRR

R_AB= 10 kΩ, 50 kΩ, 100 kΩ

DYNAMIC CHARACTERISTICS^{7, 13, 14}

Bandwidth, −3 dB

BW_1 kΩ

BW_10 kΩ

BW_50 kΩ

BW_100 kΩ

THD_W

R_AB= 1 kΩ, code = 0x20

R_AB= 10 kΩ, code = 0x20

R_AB= 50 kΩ, code = 0x20

R_AB= 100 kΩ, code = 0x20

V_A= 1 V rms, R_AB= 1 kΩ, V_B= 0 V,

f = 1 kHz

V_A= 5 V 1 LSB error band,

V_B= 0 V, measured at V_W

V_A= 5 V 1 LSB error band,

6000

600

110

kHz

Total Harmonic Distortion

Adjustment Settling Time

0.05

t_S1

μs

Power-Up Settling Time—

After Fuses Blown

Resistor Noise Voltage

INTERFACE TIMING CHARACTERISTICS^{7, 14, 15}

t_S2

μs

V_B= 0 V, measured at V_W, V_DD= 5 V

R_AB= 1 kΩ, f = 1 kHz, code = 0x20

Applies to all parts

e_{N_WB}

nV/√Hz

SCL Clock Frequency

t_BUFBus Free Time Between

Stop and Start

t_{HD; STA}Hold Time

(Repeated Start)

f_SCL

t₁

400

kHz

μs

1.3

0.6

t₂

After this period, the first clock

pulse is generated

μs

t_LOWLow Period of SCL Clock

t_HIGHHigh Period of SCL Clock

t_{SU; STA}Setup Time for

Start Condition

t₃

t₄

t₅

1.3

0.6

μs

t_{HD; DAT}Data Hold Time

t_{SU; DAT}Data Setup Time

t_FFall Time of Both SDA and

SCL Signals

t_RRise Time of Both SDA and

SCL Signals

t_{SU; STO}Setup Time for Stop Condition

OTP Program Time

t₆

t₇

t₈

0.9

μs

0.1

0.6

0.3

t₉

μs

t₁₀

t₁₁

μs

400

¹Typical values represent average readings at 25°C, V_DD= 5 V, and V_SS= 0 V.

²Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

³V_AB= V_DD, wiper (V_W) = no connect.

⁴∆R_WB/∆T = ∆R_WA/∆T. Temperature coefficient is code-dependent; see the Typical Performance Characteristics section.

⁵INL and DNL are measured at V_W. INL with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V_Wwith the RDAC configured as a

potentiometer divider similar to a voltage output DAC. V_A= V_DDand V_B= 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating

conditions.

⁶The A, B, and W resistor terminals have no limitations on polarity with respect to each other.

⁷Guaranteed by design; not subject to production test.

⁸The minimum voltage requirement on the V_IHis 0.7 × V_DD. For example, V_IHmin = 3.5 V when V_DD= 5 V. It is typical for the SCL and SDA resistors to be pulled up to V_DD

However, care must be taken to ensure that the minimum V_IHis met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.

⁹Different from the operating power supply; the power supply for OTP is used one time only.

¹⁰Different from the operating current; the supply current for OTP lasts approximately 400 ms for the one time it is needed.

¹¹See Figure 28 for the energy plot during the OTP program.

is calculated from (I_DD× V_DD). CMOS logic level inputs result in minimum power dissipation.

DISS

¹³Bandwidth, noise, and settling time depend on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth.

The highest R value results in the minimum overall power consumption.

¹⁴All dynamic characteristics use V_DD= 5 V.

¹⁵See Figure 29 for the location of the measured values.

Rev. H | Page 5 of 24

1...3 4 567 8 9...25

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与AD5273BRJZ50-REEL7相关器件

型号	品牌	获取价格	描述	数据表
AD5273EVAL	ADI	获取价格	64-Position OTP Digital Potentiometer
AD5274	ADI	获取价格	1024-/256-Position, 1% Resistor Tolerance Error, I2C Interface and 50-TP Memory Digital R
AD5274BCPZ-100-RL7	ADI	获取价格	1024-/256-Position, 1% Resistor Tolerance Error, I2C Interface and 50-TP Memory Digital Rh
AD5274BCPZ-100-RL7	ROCHESTER	获取价格	100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10, 3 X 3
AD5274BCPZ-20-RL7	ADI	获取价格	1024-/256-Position, 1% Resistor Tolerance Error, I2C Interface and 50-TP Memory Digital Rh
AD5274BCPZ-20-RL7	ROCHESTER	获取价格	20K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10, 3 X 3 M
AD5274BRMZ-100	ROCHESTER	获取价格	100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10, 3 X 4.
AD5274BRMZ-100	ADI	获取价格	1024-/256-Position, 1% Resistor Tolerance Error, I2C Interface and 50-TP Memory Digital Rh
AD5274BRMZ-100-RL7	ADI	获取价格	1024-/256-Position, 1% Resistor Tolerance Error, I2C Interface and 50-TP Memory Digital Rh
AD5274BRMZ-20	ADI	获取价格	1024-/256-Position, 1% Resistor Tolerance Error, I2C Interface and 50-TP Memory Digital Rh

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