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AD5247BKSZ5-RL7 PDF预览

AD5247BKSZ5-RL7

更新时间： 2024-02-17 05:36:46
品牌 Logo 应用领域
亚德诺 - ADI 转换器数字电位计电阻器光电二极管
页数 文件大小 规格书
20页 489K
描述
128-Position I2C-Compatible Digital Potentiometer

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AD5247BKSZ5-RL7 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：2 X 2.10 MM, ROHS COMPLIANT, MO-203AB, SC-70, 6 PIN针数：6
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.56
Is Samacsys：N其他特性：ALSO OPERATES AT 5V SUPPLY
标称带宽：1.2 kHz控制接口：2-WIRE SERIAL
转换器类型：DIGITAL POTENTIOMETERJESD-30 代码：R-PDSO-G6
JESD-609代码：e4长度：2 mm
湿度敏感等级：1功能数量：1
位置数：128端子数量：6
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP6,.08封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3/5 V认证状态：Not Qualified
电阻定律：LINEAR最大电阻容差：30%
最大电阻器端电压：5.5 V最小电阻器端电压：
座面最大高度：1.1 mm子类别：Digital Potentiometers
标称供电电压：3 V表面贴装：YES
标称温度系数：45 ppm/ °C温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40标称总电阻：5000 Ω
宽度：1.25 mmBase Number Matches：1

AD5247BKSZ5-RL7 数据手册

 浏览型号AD5247BKSZ5-RL7的Datasheet PDF文件第2页浏览型号AD5247BKSZ5-RL7的Datasheet PDF文件第3页浏览型号AD5247BKSZ5-RL7的Datasheet PDF文件第4页浏览型号AD5247BKSZ5-RL7的Datasheet PDF文件第6页浏览型号AD5247BKSZ5-RL7的Datasheet PDF文件第7页浏览型号AD5247BKSZ5-RL7的Datasheet PDF文件第8页 
Data Sheet  
AD5247  
Parameter  
DYNAMIC CHARACTERISTICS6, 8  
Symbol  
Conditions  
Min  
Typ1  
Max  
Unit  
Bandwidth –3 dB  
BW  
RAB = 10 kΩ/50 kΩ/100 kΩ,  
code = 0x40  
VA =1 V rms, f = 1 kHz, RAB = 10 kΩ  
VA = 5 V 1 LSB error band  
RWB = 5 kΩ, RS = 0  
600/100/40  
kHz  
%
µs  
Total Harmonic Distortion  
VW Settling Time (10 kΩ/50 kΩ/100 kΩ)  
Resistor Noise Voltage Density  
THDW  
tS  
eN_WB  
0.05  
2
9
nV/√Hz  
1 Typical specifications represent average readings at 25°C and VDD = 5 V.  
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper  
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.  
3 VA = VDD, wiper (VW) = no connect.  
4 INL and DNL are measured at VW, with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V.  
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.  
5 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.  
6 Guaranteed by design, not subject to production test.  
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.  
8 All dynamic characteristics use VDD = 5 V.  
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS  
VDD = 5 V 10% or 3 V 10%, VA = VDD, −40°C < TA < +125°C, unless otherwise noted.  
Table 3.  
Parameter1, 2, 3  
Symbol  
Min  
Typ 4  
Max  
Unit  
kHz  
µs  
SCL Clock Frequency  
Bus Free Time Between Stop and Start, tBUF  
Hold Time (Repeated Start), tHD;STA  
fSCL  
t1  
t2  
400  
1.3  
0.6  
1.3  
0.6  
0.6  
5
µs  
µs  
µs  
µs  
Low Period of SCL Clock, tLOW  
High Period of SCL Clock, tHIGH  
Setup Time for Repeated Start Condition, tSU;STA  
Data Hold Time, tHD;DAT  
t3  
t4  
t5  
t6  
50  
0.9  
µs  
Data Setup Time, tSU;DAT  
t7  
t8  
t9  
t10  
100  
0.6  
ns  
ns  
ns  
µs  
Fall Time of Both SDA and SCL Signals, tF  
Rise Time of Both SDA and SCL Signals, tR  
Setup Time for Stop Condition, tSU;STO  
300  
300  
1 Specifications apply to all parts.  
2 Guaranteed by design, not subject to production test.  
3 See timing diagrams (Figure 2, Figure 33, and Figure 34) for locations of measured values.  
4 Typical specifications represent average readings at 25°C and VDD = 5 V.  
5 After this period, the first clock pulse is generated.  
t8  
t2  
t9  
t6  
SCL  
t5  
t2  
t3  
t4  
t7  
t10  
t9  
t8  
SDA  
t1  
P
P
S
S
Figure 2. I2C Interface, Detailed Timing Diagram  
Rev. F | Page 5 of 20  
 
 
 
 
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