AD5247
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION
Table 1. VDD = 5 V 1ꢀ0 or 3 V 1ꢀ0; VA = +VDD; –4ꢀ°C < TA < +125°C; unless otherwise noted
Parameter
Symbol Conditions
Min Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
RWB
R-DNL
R-INL
∆RAB
∆RAB/∆T
RWB
RWB, VA = No Connect
RWB, VA = No Connect
–1.5
–4
–30
0.1
0.ꢀ5
+1.5
+4
+30
LSB
LSB
%
ppm/°C
Ω
VA = VDD, Wiper = No Connect
Code = 0x00
45
ꢀ5
300
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
DNL
INL
∆VW/∆T
VWFSE
VWZSE
–1
–1
0.1
0.2
15
–2
+1
+1
+1
LSB
LSB
ppm/°C
LSB
LSB
Code = 0x40
Code = 0xꢀF
Code = 0x00
–3
0
0
+2
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range5
VB, W
CA
GND
VDD
V
Capacitance6 A
f = 1 MHz, Measured to GND,
Code = 0x40
f = 1 MHz, Measured to GND,
Code = 0x40
45
pF
Capacitance6 W
CW
ICM
60
1
pF
nA
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance6
VA = VDD/2
VIH
VIL
VIH
VIL
IIL
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
2.4
2.1
V
V
V
V
µA
pF
0.8
0.6
1
VIN = 0 V or 5 V
CIL
5
3
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipationꢀ
VDD RANGE
IDD
PDISS
2.ꢀ
5.5
8
40
V
µA
µW
VIH = 5 V or VIL = 0 V
VIH = 5 V or VIL = 0 V, VDD = 5 V
Power Supply Sensitivity
PSSR
VDD = +5 V 10%,
Code = Midscale
0.003
0.05 %/%
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB
Total Harmonic Distortion
BW_5K
THDW
RAB = 5 kΩ, Code = 0x40
VA = 1 V rms, VB = 0 V,
f = 1 kHz
VA = 5 V, 1 LSB Error Band
RWB = 2.5 kΩ, RS = 0 Ω
1.2
MHz
0.05
1
%
µs
nV/√Hz
VW Settling Time
Resistor Noise Voltage Density
tS
eN_WB
6
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VA = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor terminals A and W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
ꢀ PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = 5 V.
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