AD5245
ELECTRICAL CHARACTERISTICS
5 kΩ VERSION
VDD = 5 V 10ꢀ or 3 V 10ꢀ, VA = VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max
+1.5
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
R-DNL
R-INL
∆RAB
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
–1.5
–4
–30
0.1
LSB
LSB
%
ppm/°C
Ω
0.ꢀ5 +4
+30
120
(∆RAB/RAB)/∆T × 106 VAB = VDD, wiper = no connect
45
50
RW
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
DNL
INL
–1.5
–1.5
0.1
0.6
15
–2.5
2
+1.5
+1.5
LSB
LSB
ppm/°C
LSB
LSB
(∆VW/VW)/∆T × 106
VWFSE
VWZSE
Code = 0x80
Code = 0xFF
Code = 0x00
–6
0
0
6
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range5
VA, VB, VW
CA, CB
GND
VDD
V
f = 1 MHz, measured to GND,
code = 0x80
Capacitance A, B6
90
pF
f = 1 MHz, measured to GND,
code = 0x80
VDD = 5.5 V
Capacitance W6
CW
IA_SD
ICM
95
0.01
1
pF
µA
nA
Shutdown Supply Currentꢀ
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
1
VA = VB = VDD/2
VIH
VIL
VIH
VIL
IIL
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
2.4
2.1
V
V
V
V
µA
pF
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance6
0.8
0.6
1
VIN = 0 V or 5 V
CIL
5
POWER SUPPLIES
Power Supply Range
Supply Current
VDD RANGE
IDD
PDISS
2.ꢀ
5.5
8
44
V
µA
µW
VIH = 5 V or VIL = 0 V
VIH = 5 V or VIL = 0 V, VDD = 5 V
VDD = +5 V 10%, code = midscale
3
Power Dissipation8
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS6, 9
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time
PSS
0.02
0.05 %/%
BW_5K
THDW
tS
RAB = 5 kΩ, code = 0x80
1.2
0.1
1
MHz
%
µs
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = 5 V, VB = 0 V, 1 LSB error band
RWB = 2.5 kΩ, RS = 0
Resistor Noise Voltage Density
eN_WB
6
nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
ꢀ Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9 All dynamic characteristics use VDD = 5 V.
Rev. B | Page 3 of 20
5秒后页面跳转
STM32F030C6芯片介绍：主要参数分析、引脚配置说明、功耗及封装
PCF8591数据手册解读：参数、引脚说明
一文带你了解ss8050参数、引脚配置、应用指南
深入解析AD7606高性能多通道模数转换器：资料手册参数分析
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
