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AD5235BRU25 PDF预览

AD5235BRU25

更新时间： 2024-01-12 20:52:25
品牌 Logo 应用领域
亚德诺 - ADI 电位器
页数 文件大小 规格书
10页 104K
描述
Nonvolatile Memory, Dual 1024 Position Digital Potentiometers

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AD5235BRU25 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP16,.25针数：16
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.47
Samacsys Description：1024-Position Digital Potentiometer其他特性：LINEAR OR LOG TAPER SETTINGS; NONVOLATILE MEMORY; CAN ALSO OPERATE FROM +/-2.25V TO +/-2.75V SUPPLY
标称带宽：0.125 kHz控制接口：3-WIRE SERIAL
转换器类型：DIGITAL POTENTIOMETERJESD-30 代码：R-PDSO-G16
JESD-609代码：e0长度：5 mm
湿度敏感等级：1功能数量：2
位置数：1024端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：240
电源：+-2.5/3/5 V认证状态：Not Qualified
电阻定律：LOGARITHMIC最大电阻容差：30%
最大电阻器端电压：5 V最小电阻器端电压：
座面最大高度：1.2 mm子类别：Digital Potentiometers
标称供电电压：5 V表面贴装：YES
标称温度系数：35 ppm/ °C温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30标称总电阻：25000 Ω
宽度：4.4 mm

AD5235BRU25 数据手册

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PRELIMINARY TECHNICAL DATA  
Nonvolatile Memory Digital Potentiometers  
AD5235  
•
•
Permanent storage of the present scratch pad RDAC register  
values into the corresponding EEMEM register  
OPERATIONAL OVERVIEW  
The AD5235 digital potentiometer is designed to operate as a true  
variable resistor replacement device for analog signals that remain  
within the terminal voltage range of VSS<VTERM<VDD. The basic  
voltage range is limited to a VDD - VSS<5.5V. Control of the digital  
potentiometer allows both scratch pad register (RDAC register)  
changes to be made, as well as 100,000 times of nonvolatile  
electrically erasable memory (EEMEM) register operations. The  
EEMEM update process takes approximately 20.2ms, during this  
time the shift register is locked preventing any changes from taking  
place. The RDY pin flags the completion of this EEMEM save.  
The EEMEM retention is designed to last 10 years without refresh.  
The scratch pad register can be changed incrementally by using the  
software controlled Increment/Decrement instruction or the Shift  
Left/Right instruction command. Once an Increment, Decrement or  
Shift command has been loaded into the shift register, subsequent  
CS strobes will repeat this command. This is useful for push button  
control applications. Alternately the scratch pad register can be  
programmed with any position value using the standard SPI serial  
interface mode by loading the representative data word. The  
scratch pad register can be loaded with the current contents of the  
nonvolatile EEMEM register under the program control. At system  
power ON, the default value of the scratch pad memory is the value  
previously saved in the EEMEM register. The factory EEMEM  
preset value is midscale 51210.  
30 bytes of user addressable electrical-erasable memory  
The serial interface of AD5235 digital potentiometer uses a 24-bit  
serial word loaded with MSB first. The format of the SPI  
compatible word is shown in Table 1. The Command Bits (Cx)  
control the operation of the digital potentiometer according to the  
command instruction shown in Table 2. The Address Bits (Ax)  
determine which register is activated. The Data Bits (Dx) are the  
values that are loaded into the decoded register. The last  
instruction executed prior to a period of no programming activity  
should be the NOP instruction. This will place the internal logic  
circuitry in a minimum power dissipation state.  
PR  
VALID  
COMMAND  
COMMAND  
+5V  
PROCESSOR  
& ADDRESS  
COUNTER  
DECODE  
R PULLUP  
CLK  
SERIAL  
REGISTER  
SDO  
GND  
CS  
SDI  
A serial data output pin is available for daisy chaining and for  
readout of the internal register contents. The serial input data  
register uses a 24-bit instruction/address/data WORD. The write-  
protect (WP) pin provides a hardware EEMEM protection feature  
disabling any changes of the present EEMEM contents.  
Figure 2. Equivalent Digital Input-Output Logic  
The equivalent serial data input and output logic is shown in figure  
2. The open drain output SDO is disabled whenever chip select CS  
is logic high. The SPI interface can be used in two slave modes  
CPHA=1, CPOL=1 and CPHA=0, CPOL=0. CPHA and CPOL  
refer to the control bits, which dictate SPI timing in the following  
microprocessors/MicroConverters: ADuC812/824, M68HC11, and  
MC68HC16R1/916R1.  
SERIAL DATA INTERFACE  
The AD5235 contains a four-wire SPI compatible digital interface  
(SDI, SDO, CS, and CLK). Key features of this interface include:  
•
•
Independently Programmable Read & Write to all registers  
Direct parallel refresh of all RDAC wiper registers from  
corresponding EEMEM registers  
Table 1. AD5235 24-bit Serial Data Word  
M
S
B
L
S
B
AD5235  
C3 C2 C1 C0 A3 A2 A1 A0  
X
X
X
X
X
X
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0  
Command bits are identified as Cx, address bits are Ax, and data bits are Dx. Command instruction codes are defined in table 2.  
REV PrD 6 NOV, 2000  
5
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the  
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara,  
CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com  
12345678...10

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