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AD5220BRMZ10 PDF预览

AD5220BRMZ10

更新时间： 2024-01-04 20:59:38
品牌 Logo 应用领域
亚德诺 - ADI 转换器数字电位计电阻器光电二极管
页数 文件大小 规格书
11页 679K
描述
Increment/Decrement Digital Potentiometer

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AD5220BRMZ10 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP8,.19针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.63
Samacsys Confidence：3Samacsys Status：Released
2D Presentation：https://componentsearchengine.com/2D/0T/154413.3.1.pngSchematic Symbol：https://componentsearchengine.com/symbol.php?partID=154413
PCB Footprint：https://componentsearchengine.com/footprint.php?partID=1544133D View：https://componentsearchengine.com/viewer/3D.php?partID=154413
Samacsys PartID：154413Samacsys Image：https://componentsearchengine.com/Images/9/AD5220BRMZ10.jpg
Samacsys Thumbnail Image：https://componentsearchengine.com/Thumbnails/3/AD5220BRMZ10.jpgSamacsys Pin Count：8
Samacsys Part Category：Integrated CircuitSamacsys Package Category：Small Outline Packages
Samacsys Footprint Name：AD5220BRMZ10Samacsys Released Date：2015-04-16 09:48:08
Is Samacsys：N其他特性：ALSO OPERATES AT 5V SUPPLY
标称带宽：0.65 kHz控制接口：INCREMENT/DECREMENT
转换器类型：DIGITAL POTENTIOMETERJESD-30 代码：S-PDSO-G8
JESD-609代码：e3长度：3 mm
湿度敏感等级：1功能数量：1
位置数：128端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP8,.19封装形状：SQUARE
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3/5 V认证状态：Not Qualified
电阻定律：LINEAR最大电阻容差：30%
最大电阻器端电压：5.5 V最小电阻器端电压：
座面最大高度：1.1 mm子类别：Digital Potentiometers
标称供电电压：3 V表面贴装：YES
技术：CMOS标称温度系数：800 ppm/ °C
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
标称总电阻：10000 Ω宽度：3 mm
Base Number Matches：1

AD5220BRMZ10 数据手册

 浏览型号AD5220BRMZ10的Datasheet PDF文件第1页浏览型号AD5220BRMZ10的Datasheet PDF文件第3页浏览型号AD5220BRMZ10的Datasheet PDF文件第4页浏览型号AD5220BRMZ10的Datasheet PDF文件第5页浏览型号AD5220BRMZ10的Datasheet PDF文件第6页浏览型号AD5220BRMZ10的Datasheet PDF文件第7页 
AD5220–SPECIFICATIONS  
(VDD = +3 V ؎ 10% or +5 V ؎ 10%, VA = +VDD, VB = 0 V, –40؇C < TA < +85؇C unless  
otherwise noted)  
ELECTRICAL CHARACTERISTICS  
Parameter  
Symbol  
Conditions  
Min  
Typ1  
Max  
Units  
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs  
Resistor Differential NL2  
R-DNL  
RWB, VA = NC, RAB = 10 kΩ  
RWB, VA = NC, RAB = 50 kΩ or 100 kΩ  
RWB, VA = NC, RAB = 10 kΩ  
RWB, VA = NC, RAB = 50 kΩ or 100 kΩ  
TA = +25°C  
–1  
–0.5  
–1  
–0.5  
–30  
±0.4  
±0.1  
±0.5  
±0.1  
+1  
+0.5  
+1  
+0.5  
+30  
LSB  
LSB  
LSB  
LSB  
%
Resistor Nonlinearity2  
R-INL  
Nominal Resistor Tolerance  
Resistance Temperature Coefficient  
Wiper Resistance  
∆R  
∆RAB/∆T  
RW  
VAB = VDD, Wiper = No Connect  
IW = VDD/R, VDD = +3 V or +5 V  
800  
40  
ppm/°C  
Ω
100  
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs  
Resolution  
N
INL  
7
–1  
–0.5  
–1  
–0.5  
Bits  
Integral Nonlinearity3  
RAB = 10 kΩ  
RAB = 50 kΩ, 100 kΩ  
RAB = 10 kΩ  
RAB = 50 kΩ, 100 kΩ  
Code = 40H  
Code = 7FH  
±0.5  
±0.2  
±0.4  
±0.1  
20  
+1  
+0.5  
+1  
LSB  
LSB  
LSB  
LSB  
ppm/°C  
LSB  
LSB  
Differential Nonlinearity Error3  
DNL  
+0.5  
Voltage Divider Temperature Coefficient ∆VW/∆T  
Full-Scale Error  
Zero-Scale Error  
VWFSE  
VWZSE  
–2  
0
–0.5  
+0.5  
0
+1  
Code = 00H  
RESISTOR TERMINALS  
Voltage Range4  
VA, VB, VW  
CA, CB  
CW  
0
VDD  
V
Capacitance5 A, B  
f = 1 MHz, Measured to GND, Code = 40H  
f = 1 MHz, Measured to GND, Code = 40H  
VA = VB = VW  
10  
48  
7.5  
pF  
pF  
nA  
Capacitance5 W  
Common-Mode Leakage  
ICM  
DIGITAL INPUTS AND OUTPUTS  
Input Logic High  
Input Logic Low  
VIH  
VIL  
IIL  
VDD = +5 V/+3 V  
VDD = +5 V/+3 V  
VIN = 0 V or +5 V  
2.4/2.1  
2.7  
V
V
µA  
pF  
0.8/0.6  
±1  
Input Current  
Input Capacitance5  
CIL  
5
POWER SUPPLIES  
Power Supply Range  
Supply Current  
VDD  
IDD  
PDISS  
PSS  
5.5  
40  
200  
0.015  
V
µA  
µW  
%/%  
VIH = +5 V or VIL = 0 V, VDD = +5 V  
VIH = +5 V or VIL = 0 V, VDD = +5 V  
15  
75  
0.004  
Power Dissipation6  
Power Supply Sensitivity  
DYNAMIC CHARACTERISTICS5, 7, 8  
Bandwidth –3 dB  
BW_10K  
BW_50K  
RAB = 10 kΩ, Code = 40H  
RAB = 50 kΩ, Code = 40H  
650  
142  
69  
kHz  
kHz  
kHz  
%
BW_100K RAB = 100 kΩ, Code = 40H  
THDW  
tS  
Total Harmonic Distortion  
VW Settling Time  
VA =1 V rms + 2.5 V dc, VB = 2.5 V dc, f = 1 kHz  
VA = VDD, VB = 0 V, 50% of Final Value,  
10K/50K/100K  
0.002  
0.6/3/6  
14  
µs  
nV/√Hz  
Resistor Noise Voltage  
eNWB  
RWB = 5 kΩ, f = 1 kHz  
INTERFACE TIMING CHARACTERISTICS Applies to All Parts5, 9  
Input Clock Pulsewidth  
CS to CLK Setup Time  
CS Rise to Clock Hold Time  
U/D to Clock Fall Setup Time  
tCH, tCL  
tCSS  
tCSH  
Clock Level High or Low  
25  
20  
20  
10  
ns  
ns  
ns  
ns  
tUDS  
NOTES  
1Typicals represent average readings at +25°C and VDD = +5 V.  
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper  
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 29 test circuit.  
3INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.  
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 28 test circuit.  
4Resistor terminals A, B, W have no limitations on polarity with respect to each other.  
5Guaranteed by design and not subject to production test.  
6PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.  
7Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band-  
width. The highest R value results in the minimum overall power consumption.  
8All dynamic characteristics use VDD = +5 V.  
9See timing diagrams for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level  
of 1.6 V. Switching characteristics are measured using both VDD = +3 V or +5 V.  
Specifications subject to change without notice.  
–2–  
REV.  
A
1234567...11

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