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AD5207BRU50-REEL7 PDF预览

AD5207BRU50-REEL7

更新时间： 2024-01-07 02:55:39
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管
页数 文件大小 规格书
17页 1314K
描述
DUAL 50K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14, 1.10 MM HEIGHT, TSSOP-14

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AD5207BRU50-REEL7 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP,针数：14
Reach Compliance Code：unknown风险等级：5.84
Is Samacsys：N其他特性：IT CAN ALSO OPERATE FROM A +/-2.2V TO +/-2.7V DUAL SUPPLY
标称带宽：0.125 kHz控制接口：3-WIRE SERIAL
转换器类型：DIGITAL POTENTIOMETERJESD-30 代码：R-PDSO-G14
JESD-609代码：e0长度：5 mm
湿度敏感等级：1功能数量：2
位置数：256端子数量：14
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：240认证状态：COMMERCIAL
电阻定律：LINEAR最大电阻容差：30%
最大电阻器端电压：5 V最小电阻器端电压：
座面最大高度：1.2 mm标称供电电压：5 V
表面贴装：YES标称温度系数：500 ppm/ °C
温度等级：AUTOMOTIVE端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
标称总电阻：50000 Ω宽度：4.4 mm
Base Number Matches：1

AD5207BRU50-REEL7 数据手册

 浏览型号AD5207BRU50-REEL7的Datasheet PDF文件第1页浏览型号AD5207BRU50-REEL7的Datasheet PDF文件第2页浏览型号AD5207BRU50-REEL7的Datasheet PDF文件第3页浏览型号AD5207BRU50-REEL7的Datasheet PDF文件第5页浏览型号AD5207BRU50-REEL7的Datasheet PDF文件第6页浏览型号AD5207BRU50-REEL7的Datasheet PDF文件第7页 
AD5207  
Parameter  
Symbol  
Conditions  
Min  
Typ1  
Max  
Unit  
INTERFACE TIMING  
CHARACTERISTICS  
Applies to All Parts6, 11  
Input Clock Pulsewidth  
Data Setup Time  
tCH, tCL  
tDS  
tDH  
tPD  
tCSS  
tCSW  
tCSH0  
tCSH1  
tCS1  
Clock Level High or Low  
10  
5
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Data Hold Time  
CLK to SDO Propagation Delay12  
CS Setup Time  
RL = 1 kΩ to 5 V, CL < 20 pF  
1
25  
10  
10  
0
0
10  
CS High Pulsewidth  
CLK Fall to CS Fall Hold Time  
CLK Fall to CS Rise Hold Time  
CS Rise to Clock Rise Setup  
NOTES  
1 Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.  
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper  
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both VDD = 5 V,  
VSS = 0 V.  
3 VAB = VDD, Wiper (VW) = No connect.  
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL  
specification limits of 1 LSB maximum are Guaranteed Monotonic operating conditions.  
5 Resistor Terminals A, B, W have no limitations on polarity with respect to each other.  
6 Guaranteed by design and not subject to production test.  
7 Measured at the AX terminals. All AX terminals are open-circuited in shut-down mode.  
8 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.  
9 All dynamic characteristics use VDD = 5 V, VSS = 0 V.  
10 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.  
11 See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of  
1.5 V. Switching characteristics are measured using VDD = 5 V.  
12 Propagation delay depends on value of VDD, RL, and CL; see applications text.  
The AD5207 contains 474 transistors. Die Size: 67 mil × 69 mil, 4623 sq. mil.  
Specifications subject to change without notice.  
1
SDI  
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0  
0
1
CLK  
0
1
RDAC REGISTER LOAD  
CS  
0
V
OUT  
Figure 1a. Timing Diagram  
1
0
SDI  
(DATA IN)  
Ax OR Dx  
Ax OR Dx  
tDS  
tDH  
1
0
SDO  
(DATA OUT)  
'
'
A'x OR D'x  
tCH  
A x OR D x  
tPD_MAX  
tCS1  
1
0
CLK  
tCSH0  
tCSS  
tCL  
tCSH1  
1
0
CS  
tCSW  
tS  
V
OUT  
DD  
V
0V  
؎1LSB ERROR BAND  
؎1LSB  
Figure 1b. Detail Timing Diagram  
–3–  
REV. 0  
1234567...17

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