Datasheet > AD5207

AD5207

更新时间： 2022-12-11 21:11:15

品牌	Logo	应用领域
亚德诺 - ADI		数字电位计
页数	文件大小	规格书
16页	660K
描述
2-Channel, 256-Position Digital Potentiometer

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AD5207 数据手册

AD5207

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

INTERFACE TIMING

CHARACTERISTICS

Applies to All Parts^{6, 11}

Input Clock Pulsewidth

Data Setup Time

t_CH, t_CL

t_DS

t_DH

t_PD

t_CSS

t_CSW

t_CSH0

t_CSH1

t_CS1

Clock Level High or Low

Data Hold Time

CLK to SDO Propagation Delay¹²

CS Setup Time

R_L= 1 kΩ to 5 V, C_L< 20 pF

CS High Pulsewidth

CLK Fall to CS Fall Hold Time

CLK Fall to CS Rise Hold Time

CS Rise to Clock Rise Setup

NOTES

¹Typicals represent average readings at 25°C and V_DD= 5 V, V_SS= 0 V.

²Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I _W= V_DD/R for both V_DD= 5 V,

V_SS= 0 V.

³V_AB= V_DD, Wiper (V_W) = No connect.

⁴INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V_A= V_DDand V_B= 0 V. DNL

specification limits of 1 LSB maximum are Guaranteed Monotonic operating conditions.

⁵Resistor Terminals A, B, W have no limitations on polarity with respect to each other.

⁶Guaranteed by design and not subject to production test.

⁷Measured at the A_Xterminals. All A_Xterminals are open-circuited in shut-down mode.

⁸P_DISSis calculated from (I_DD× V_DD). CMOS logic level inputs result in minimum power dissipation.

⁹All dynamic characteristics use V_DD= 5 V, V_SS= 0 V.

¹⁰Measured at a V_Wpin where an adjacent V_Wpin is making a full-scale voltage change.

¹¹See timing diagram for location of measured values. All input control voltages are specified with t_R= t_F= 2 ns (10% to 90% of 3 V) and timed from a voltage level of

1.5 V. Switching characteristics are measured using V_DD= 5 V.

¹²Propagation delay depends on value of V_DD, R_L, and C_L; see applications text.

The AD5207 contains 474 transistors. Die Size: 67 mil × 69 mil, 4623 sq. mil.

Specifications subject to change without notice.

SDI

A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

CLK

RDAC REGISTER LOAD

OUT

Figure 1a. Timing Diagram

SDI

(DATA IN)

Ax OR Dx

t_DS

t_DH

SDO

(DATA OUT)

A'x OR D'x

t_CH

A x OR D x

t_{PD_MAX}

t_CS1

CLK

t_CSH0

t_CSS

t_CL

t_CSH1

t_CSW

t_S

OUT

؎1LSB ERROR BAND

؎1LSB

Figure 1b. Detail Timing Diagram

–3–

REV. 0

1 234 5 6 7...16

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