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AD5206BRZ50 PDF预览

AD5206BRZ50

更新时间: 2024-02-06 10:14:57
品牌 Logo 应用领域
亚德诺 - ADI 转换器电位器数字电位计电阻器光电二极管
页数 文件大小 规格书
20页 371K
描述
4-/6-Channel Digital Potentiometers

AD5206BRZ50 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:24
Reach Compliance Code:unknown风险等级:5.74
其他特性:CAN ALSO OPERATE FROM +/-2.3V TO +/-2.7V SUPPLY标称带宽:0.137 kHz
控制接口:3-WIRE SERIAL转换器类型:DIGITAL POTENTIOMETER
JESD-30 代码:R-PDSO-G24JESD-609代码:e3
长度:15.4 mm湿度敏感等级:1
标称负供电电压:-2.5 V功能数量:6
位置数:256端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:COMMERCIAL
电阻定律:LINEAR最大电阻容差:30%
最大电阻器端电压:2.7 V最小电阻器端电压:-2.3 V
座面最大高度:2.65 mm标称供电电压:2.5 V
表面贴装:YES标称温度系数:700 ppm/ °C
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
标称总电阻:50000 Ω宽度:7.5 mm
Base Number Matches:1

AD5206BRZ50 数据手册

 浏览型号AD5206BRZ50的Datasheet PDF文件第1页浏览型号AD5206BRZ50的Datasheet PDF文件第2页浏览型号AD5206BRZ50的Datasheet PDF文件第3页浏览型号AD5206BRZ50的Datasheet PDF文件第5页浏览型号AD5206BRZ50的Datasheet PDF文件第6页浏览型号AD5206BRZ50的Datasheet PDF文件第7页 
AD5204/AD5206  
Parameter  
Symbol  
Conditions  
Min  
Typ1  
Max  
Unit  
INTERFACE TIMING CHARACTERISTICS7, 11, 12  
Input Clock Pulse Width  
Data Setup Time  
Data Hold Time  
CLK-to-SDO Propagation Delay13  
tCH, tCL  
tDS  
tDH  
tPD  
tCSS  
Clock level high or low  
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RL = 2 kΩ , CL < 20 pF  
1
1ꢀ0  
CS Setup Time  
1ꢀ  
40  
90  
0
CS High Pulse Width  
tCSW  
tRS  
tCSH0  
tCSH1  
tCS1  
Reset Pulse Width  
CLK Fall to CS Fall Setup  
CLK Fall to CS Rise Hold Time  
CS Rise to Clock Rise Setup  
0
10  
1 Typicals represent average readings at 2ꢀ°C and VDD = ꢀ V.  
2 Applies to all VRs.  
3 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.  
R-DNL measures the relative step change from the ideal position between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 28.  
I
W = VDD/R for both VDD = 3 V and VDD = ꢀ V.  
4 VAB = VDD, wiper (VW) = no connect.  
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits  
of 1 LSB maximum are guaranteed monotonic at operating conditions. See the test circuit in Figure 27.  
6 Resistor Terminal A, Terminal B, and Wiper W have no limitations on polarity with respect to each other.  
7 Guaranteed by design and not subject to production test.  
8 Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.  
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.  
10 All dynamic characteristics use VDD = ꢀ V.  
11 Applies to all parts.  
12 See the timing diagrams (Figure 3 to Figure ꢀ) for the location of the measured values. All input control voltages are specified with tR = tF = 2.ꢀ ns (10% to 90% of 3 V)  
and timed from a voltage level of 1.ꢀ V. Switching characteristics are measured using both VDD = 3 V and VDD = ꢀ V.  
13 The propagation delay depends on the values of VDD, RL, and CL (see the Operation section).  
Rev. C | Page 4 of 20  
 

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