Datasheet > AD5206BRZ102

AD5206BRZ102

更新时间： 2024-01-04 14:44:07

品牌	Logo	应用领域
亚德诺 - ADI		光电二极管转换器
页数	文件大小	规格书
20页	475K
描述
IC,DIGITAL POTENTIOMETER,SOP,24PIN,PLASTIC

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AD5206BRZ102 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
Reach Compliance Code：	compliant	风险等级：	5.84
转换器类型：	DIGITAL POTENTIOMETER	JESD-30 代码：	R-PDSO-G24
端子数量：	24	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP24,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	3/5 V	认证状态：	Not Qualified
子类别：	Digital Potentiometers	表面贴装：	YES
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
Base Number Matches：	1

AD5206BRZ102 数据手册

AD5204/AD5206

Parameter

Symbol

THD_W

t_S

Conditions

Min

Typ¹

Max

Unit

μs

Total Harmonic Distortion

VW Settling Time

V_A= 1./1/ V rms, V_B= 0 V dc, f = 1 kHz

V_A= 5 V, V_B= 0 V, 1 LSB error band

0.00/

2ꢀ9ꢀ18

(10 kΩꢀ50 kΩꢀ100 kΩ)

Resistor Noise Voltage

e_{N_WB}

R_WB= 5 kΩ , f = 1 kHz, PR = 0

Clock level high or low

nVꢀ√Hz

INTERFACE TIMING CHARACTERISTICS^{7, 11, 12}

Input Clock Pulse Width

Data Setup Time

Data Hold Time

CLK-to-SDO Propagation Delay¹³

t_CH, t_CL

t_DS

t_DH

t_PD

t_CSS

R_L= 2 kΩ , C_L< 20 pF

150

CS Setup Time

CS High Pulse Width

t_CSW

t_RS

t_CSH0

t_CSH1

t_CS1

Reset Pulse Width

CLK Fall to CS Fall Setup

CLK Fall to CS Rise Hold Time

CS Rise to Clock Rise Setup

¹Typicals represent average readings at 25°C and V_DD= 5 V.

²Applies to all VRs.

³Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from the ideal position between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 28.

I_W= V_DDꢀR for both V_DD= 3 V and V_DD= 5 V.

^/V_AB= V_DD, wiper (V_W) = no connect.

⁵INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output DAC. V_A= V_DDand V_B= 0 V. DNL specification limits

of 1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 27.

⁶Resistor Terminal A, Terminal B, and Wiper W have no limitations on polarity with respect to each other.

⁷Guaranteed by design and not subject to production test.

⁸Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.

⁹P_DISSis calculated from (I_DD× V_DD). CMOS logic level inputs result in minimum power dissipation.

¹⁰All dynamic characteristics use V_DD= 5 V.

¹¹Applies to all parts.

¹²See the timing diagrams (Figure 3 to Figure 5) for the location of the measured values. All input control voltages are specified with t_R= t_F= 2.5 ns (10% to 90% of 3 V)

and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V_DD= 3 V and V_DD= 5 V.

¹³The propagation delay depends on the values of V_DD, R_L, and C_L(see the Operation section).

Rev. A | Page / of 20

1 2 345 6 7...20

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