AD5204/AD5206–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (V = +5 V ؎ 10% or +3 V ؎ 10%, V = 0 V, V = +V , V = 0 V, –40؇C < T < +85؇C
unless otherwise noted.)
DD
SS
A
DD
B
A
Parameter
Symbol
Conditions
Min
Typ1
Max
Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL2
Resistor Nonlinearity Error2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Nominal Resistance Match
Wiper Resistance
R-DNL
R-INL
∆RAB
∆RAB/∆T
∆R/RAB
RW
RWB, VA = No Connect
RWB, VA = No Connect
TA = +25°C
VAB = VDD, Wiper = No Connect
CH1 to 2, 3, 4, or 5, 6; VAB = VDD
IW = 1 V/R, VDD = +5 V
–1
–2
–30
±1/4
±1/2
+1
+2
+30
LSB
LSB
%
ppm/°C
%
700
0.25
50
1.5
100
Ω
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
Resolution
N
DNL
INL
8
–1
–2
Bits
LSB
LSB
ppm/°C
LSB
Differential Nonlinearity4
±1/4
±1/2
15
–1
+1
+1
+2
Integral Nonlinearity4
Voltage Divider Temperature Coefficient ∆VW/∆T
Full-Scale Error
Zero-Scale Error
Code = 40H
Code = 7FH
Code = 00H
VWFSE
VWZSE
–2
0
0
+2
LSB
RESISTOR TERMINALS
Voltage Range5
VA, VB, VW
CA, CB
CW
IA_SD
ICM
VSS
VDD
V
Capacitance6 Ax, Bx
Capacitance6 Wx
f = 1 MHz, Measured to GND, Code = 40H
f = 1 MHz, Measured to GND, Code = 40H
45
60
0.01
1
pF
pF
µA
nA
Shutdown Current7
Common-Mode Leakage
5
VA = VB = VW = 0, VDD = +2.7 V, VSS = –2.5 V
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
VIH
VIL
VOH
VOL
IIL
VDD = +5 V/+3 V
VDD = +5 V/+3 V
RPULL–UP = 1 kΩ to +5 V
IOL = 1.6 mA, VLOGIC = +5 V
VIN = 0 V or +5 V
2.4/2.1
4.9
V
V
V
V
µA
pF
0.8/0.6
0.4
±1
Input Current
Input Capacitance6
CIL
5
POWER SUPPLIES
Power Single Supply Range
Power Dual Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation8
VDD Range
VDD/SS Range
IDD
ISS
PDISS
VSS = 0 V
2.7
±2.3
5.5
±2.7
60
60
0.3
V
V
µA
µA
mW
%/%
VIH = +5 V or VIL = 0 V
VSS = –2.5 V, VDD = +2.7 V
VIH = +5 V or VIL = 0 V
∆VDD = +5 V ± 10%
12
12
Power Supply Sensitivity
PSS
0.0002 0.005
DYNAMIC CHARACTERISTICS6, 9
Bandwidth –3 dB
BW_10K
BW_50K
BW_100K
THDW
tS
RAB = 10 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
VA = 1.414 V rms, VB = 0 V dc, f = 1 kHz
VA = 5 V, VB = 0 V, ±1 LSB Error Band
RWB = 5 kΩ, f = 1 kHz, PR = 0
721
137
69
0.004
2/9/18
9
kHz
kHz
kHz
%
µs
nV/√Hz
Total Harmonic Distortion
VW Settling Time (10K/50K/100K)
Resistor Noise Voltage
eN_WB
INTERFACE TIMING CHARACTERISTICS Applies to All Parts6, 10
Input Clock Pulsewidth
Data Setup Time
tCH, tCL
tDS
tDH
tPD
tCSS
tCSW
tRS
tCSH0
tCSH1
tCS1
Clock Level High or Low
20
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Hold Time
CLK to SDO Propagation Delay11
CS Setup Time
RL = 2 kΩ, CL < 20 pF
1
150
15
40
90
0
0
10
CS High Pulsewidth
Reset Pulsewidth
CLK Fall to CS Fall Setup
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
NOTES
1Typicals represent average readings at +25°C and VDD = +5 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 23 test circuit. I W = VDD/R
for both VDD = +3 V or VDD = +5 V.
3VAB = VDD, Wiper (VW) = No connect.
4INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 22 test circuit.
–2–
REV. 0
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