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AD5203AR10

更新时间： 2024-01-11 09:49:30
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管转换器电阻器
页数 文件大小 规格书
13页 942K
描述
10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24, SOIC-24

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AD5203AR10 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOIC-24
针数：24Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.66其他特性：REST 3 RESISTOR ARRAY VALUES ARE : 10000OHMS
标称带宽：0.6 kHz控制接口：3-WIRE SERIAL
转换器类型：DIGITAL POTENTIOMETERJESD-30 代码：R-PDSO-G24
JESD-609代码：e0长度：15.4 mm
功能数量：1位置数：64
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：220
认证状态：Not Qualified电阻定律：LINEAR
最大电阻容差：30%最大电阻器端电压：5.5 V
最小电阻器端电压：座面最大高度：2.65 mm
标称供电电压：3 V表面贴装：YES
标称温度系数：700 ppm/ °C温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30标称总电阻：10000 Ω
宽度：7.5 mmBase Number Matches：1

AD5203AR10 数据手册

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AD5203  
NOTES  
1Typicals represent average readings at +25°C and VDD = +5 V.  
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-  
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27 test circuit. I W = VDD/R  
for both VDD = +3 V or VDD = +5 V.  
3VAB = VDD, Wiper (VW) = No connect.  
4INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V.  
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 26 test circuit.  
5Resistor terminals A, B, W have no limitations on polarity with respect to each other.  
6Guaranteed by design and not subject to production test.  
7Measured at the AX terminals. All AX terminals are open-circuited in shutdown mode.  
8Worst case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic. See Figure 19 for a plot of I DD vs. logic voltage  
inputs result in minimum power dissipation.  
9PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.  
10All dynamic characteristics use VDD = +5 V.  
11Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.  
12See timing diagrams for location of measured values. All input control voltages are specified with t R = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level  
of 1.6 V. Switching characteristics are measured using both VDD = +3 V or +5 V. Input logic should have a 1 V/µs minimum slew rate.  
13Propagation delay depends on value of VDD, RL and CL. See Operation section.  
ABSOLUTE MAXIMUM RATINGS*  
(TA = +25°C, unless otherwise noted)  
1
SDI  
A1 A0 D5 D4 D3 D2 D1 D0  
0
1
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +8 V  
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD  
IAB, IAW, IBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA  
Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V  
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C  
Maximum Junction Temperature (TJ MAX) . . . . . . . .+150°C  
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C  
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C  
Package Power Dissipation . . . . . . . . . . . . . . (TJ max–TA)/θJA  
Thermal Resistance θJA  
CLK  
0
1
DAC REGISTER LOAD  
CS  
0
V
DD  
V
OUT  
0V  
Figure 1a. Timing Diagram  
1
0
SDI  
(DATA IN)  
Ax OR Dx  
Ax OR Dx  
tDS  
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W  
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W  
TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W  
tDH  
1
0
SDO  
(DATA OUT)  
A'x OR D'x  
A'x OR D'x  
*Stresses above those listed under Absolute Maximum Ratings may cause perma-  
nent damage to the device. This is a stress rating only; functional operation of the  
device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect device reliability.  
tPD  
tPD  
MIN  
MAX  
tCH  
tCS1  
1
0
CLK  
tCL  
tCSH  
tCSS  
1
0
tCSW  
CS  
Table I. Serial-Data Word Format  
tS  
؎1 LSB  
V
DD  
ADDR  
B7  
DATA  
B5  
V
OUT  
؎ 1 LSB ERROR BAND  
0V  
B6  
B4  
B3  
B2  
B1  
B0  
Figure 1b. Detail Timing Diagram  
A1  
A0  
D5  
D4  
D3  
D2  
D1  
D0  
LSB  
20  
MSB LSB  
MSB  
27 26  
25  
tRS  
1
RS  
0
tS  
؎1 LSB  
V
DD  
V
OUT  
؎1 LSB ERROR BAND  
0V  
Figure 1c. Reset Timing Diagram  
CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily  
accumulate on the human body and test equipment and can discharge without detection.  
Although the AD5203 features proprietary ESD protection circuitry, permanent damage may  
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD  
precautions are recommended to avoid performance degradation or loss of functionality.  
WARNING!  
ESD SENSITIVE DEVICE  
REV. 0  
–3–  
1234567...13

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