AD5200/AD5201–SPECIFICATIONS
(VDD = 5 V ꢁ 10%, or 3 V ꢁ 10%, VSS = 0 V, VA = +VDD, VB = 0 V,
–40ꢂC < T < +85ꢂC unless otherwise noted.)
AD5200 ELECTRICAL CHARACTERISTICS
A
Parameter
Symbol
Conditions
Min Typ1 Max
Unit
DCCHARACTERISTICSRHEOSTATMODE
2
ResistorDifferentialNonlinearity
R-DNL
R-INL
∆RAB
RWB, VA = No Connect
RWB, VA = No Connect
TA = 25°C
–1
–2
–30
0.25 +1
0.5 +2
LSB
LSB
%
2
ResistorIntegralNonlinearity
3
NominalResistorTolerance
+30
ResistanceTemperatureCoefficient
WiperResistance
R
RW
AB/∆T
VAB = VDD, Wiper = No Connect
VDD = 5 V
500
50
ppm/°C
Ω
100
DCCHARACTERISTICSPOTENTIOMETERDIVIDERMODE(SpecificationsapplytoallVRs.)
Resolution
DifferentialNonlinearity
IntegralNonlinearity
N
DNL
INL
8
–1
–2
Bits
LSB
LSB
4
1/4 +1
1/2 +2
4
VoltageDividerTemperatureCoefficient
Full-ScaleError
Zero-ScaleError
∆VW/∆T
VWFSE
VWZSE
Code = 80 H
Code = FF H
Code = 00 H
5
ppm/°C
LSB
LSB
–1.5 –0.5
0
0
+0.5 +1.5
RESISTORTERMINALS
VoltageRange 5
VA, B, W
CA, B
CW
IDD_SD
ICM
VSS
VDD
V
Capacitance 6 A,B
f = 1 MHz, Measured to GND, Code = 80
f = 1 MHz, Measured to GND, Code = 80
VDD = 5.5 V
45
60
0.01
1
pF
pF
µA
nA
H
H
Capacitance 6 W
ShutdownSupplyCurrent
Common-ModeLeakage
7
5
VA = VB = VDD/2
DIGITALINPUTSANDOUTPUTS
InputLogicHigh
InputLogicLow
InputLogicHigh
InputLogicLow
VIH
VIL
VIH
VIL
IIL
2.4
2.1
V
V
V
V
µA
pF
0.8
VDD = 3 V, VSS = 0 V
VDD = 3 V, VSS = 0 V
VIN = 0 V or 5 V
0.6
1
InputCurrent
InputCapacitance
6
CIL
5
POWERSUPPLIES
LogicSupply
VLOGIC
VDD RANGE
VDD/SS RANGE
IDD
ISS
PDISS
2.7
–0.3
2.3
5.5
5.5
2.7
40
40
0.2
V
V
V
µA
µA
mW
PowerSingle-SupplyRange
PowerDual-SupplyRange
PositiveSupplyCurrent
NegativeSupplyCurrent
PowerDissipation 8
VSS = 0 V
VIH = +5 V or VIL = 0 V
VSS = –5 V
VIH = +5 V or VIL = 0 V, VDD = +5 V, VSS = 0 V
15
15
PowerSupplySensitivity
PSS
∆VDD = +5 V 10%, Code = Midscale
–0.01 0.001 +0.01 %/%
6,9
DYNAMICCHARACTERISTICS
Bandwidth–3dB
BW_10 kΩ
BW_50 kΩ
THDW
tS
RAB = 10 kΩ, Code = 80 H
RAB = 50 kΩ, Code = 80 H
VA = 1 V rms, VB = 0 V, f = 1 kHz, R AB = 10 kΩ
VA = 5 V, VB = 0 V, 1 LSB Error Band
RWB = 5 kΩ, RS = 0
600
100
0.003
2/9
kHz
kHz
%
µs
nV√Hz
TotalHarmonicDistortion
VW Settling Time (10 kΩ/50 kΩ)
Resistor Noise Voltage Density
eN_WB
9
NOTES
1Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both VDD = +2.7 V,
VSS = –2.7 V.
3VAB = VDD, Wiper (VW) = No connect.
4INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL
specification limits of 1 LSB maximum are Guaranteed Monotonic operating conditions.
5Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6Guaranteed by design and not subject to production test.
7Measured at the A terminal. A terminal is open-circuited in shutdown mode.
8PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9All dynamic characteristics use VDD = 5 V, VSS = 0 V.
Specifications subject to change without notice.
REV. D
–2–
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