AD5162
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS: 2.5 kΩ VERSION
VDD = 5 V 10%, or 3 V 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ 1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
R-DNL
R-INL
∆RAB
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
−2
−14
−20
0.1
2
+2
+14
+55
LSB
LSB
%
ppm/°C
Ω
(∆RAB/RAB )/∆T VAB = VDD, wiper = no connect
RWB
35
160
Code = 0x00, VDD = 5 V
200
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE4
Differential Nonlinearity5
Integral Nonlinearity5
DNL
INL
−1.5
−2
0.1
0.6
+1.5
+2
LSB
LSB
Voltage Divider Temperature
Coefficient
(∆VW/VW)/∆T
Code = 0x80
15
ppm/°C
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range6
VWFSE
VWZSE
Code = 0xFF
Code = 0x00
−14
0
−5.5
4.5
0
12
LSB
LSB
VA, VB, VW
CA, CB
GND
VDD
V
pF
Capacitance A, B7
f = 1 MHz, measured to GND,
code = 0x80
f = 1 MHz, measured to GND,
code = 0x80
45
60
1
Capacitance W7
CW
ICM
pF
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance7
POWER SUPPLIES
VA = VB = VDD/2
nA
VIH
VIL
VIH
VIL
IIL
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
2.4
2.1
V
V
V
V
µA
pF
0.8
0.6
1
VIN = 0 V or 5 V
CIL
5
Power Supply Range
Supply Current
VDD RANGE
IDD
PDISS
2.7
5.5
6
30
V
µA
µW
VIH = 5 V or VIL = 0 V
VIH = 5 V or VIL = 0 V, VDD = 5 V
VDD = 5 V 10%, code = midscale
3.5
Power Dissipation8
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS9
Bandwidth, −3 dB
Total Harmonic Distortion
VW Settling Time
PSS
0.02
0.08
%/%
BW
THDW
tS
Code = 0x80
4.8
0.1
1
MHz
%
µs
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = 5 V, VB = 0 V, 1 LSB error band
RWB = 1.25 kΩ, RS = 0
Resistor Noise Voltage Density
eN_WB
3.2
nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3 VA = VDD, VB = 0 V, wiper (VW) = no connect.
4 Specifications apply to all VRs.
5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V.
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7 Guaranteed by design, but not subject to production test.
8 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9 All dynamic characteristics use VDD = 5 V.
Rev. C | Page 3 of 20