AD1862
tributed by the voltage reference circuitry. The proper choice for
this capacitor is a tantalum type with value of 10 µF or more. This
capacitor should be connected to the package pins as closely as
possible. This will minimize the effects of parasitic inductance of
the leads and connections circuit connections.
Analog Circuit Considerations
GRO UND ING RECO MMEND ATIO NS
T he AD1862 has two ground pins, designated analog ground
(AGND) and digital ground (DGND). T he analog ground pin
is the “high-quality” ground reference for the device. T he ana-
log ground pin should be connected to the analog common
point in the system. T he reference bypass capacitor, the nonin-
verting terminal of the current-to-voltage conversion op amp,
and any output loads should be connected to this point. T he
digital ground pin returns ground current from the digital logic
portions of the AD1862 circuitry. T his pin should be connected
to the digital common point in the system.
16
15
14
1
2
3
C2
C1
–12V
ANALOG
SUPPLY
+
AD1862
+
13
12
11
10
9
4
5
6
TOP VIEW
(Not to
Scale)
As illustrated in Figure 7, AGND and DGND should be con-
nected together at one point in the system.
7
8
NOTE:
PIN 1 IS "HIGH QUALITY" RETURN
FOR BIAS CAP.
1
2
3
4
5
6
7
8
16
15
14
13
Figure 8. Noise Reduction Capacitors
AD1862
TOP VIEW
Capacitor C2 is connected between the pin labeled NR2 and the
negative analog supply, –VS. T his capacitor reduces the portion
of output noise contributed by the control amplifier circuitry.
C2 should be chosen to be a tantalum capacitor with a value of
about 1 µF. Again, the connections between the AD1862 and
C2 should be made as short as possible.
(Not to Scale) 12
11
10
9
AGND
DGND
T he recommended values for C1 and C2 are 10 µF and 1 µF,
respectively. T he ratio between C1 and C2 should be approxi-
mately 10. Additional noise reduction can be gained by choos-
ing slightly higher values for C1 and C2 such as 22 µF and
2.2 µF. Figure 2 illustrates the noise performance of the
AD1862 with 10 µF and 1 µF.
Figure 7. Grounding and Bypassing Recom m endations
P O WER SUP P LIES AND D ECO UP LING
T he AD1862 has four power supply input pins. ±VS provide the
supply voltages which operate the linear portions of the DAC in-
cluding the voltage reference and control amplifier. T he ±VS
supplies are designed to operate with ±12 volts.
EXTERNAL AMP LIFIER CO NNECTIO NS
T he AD1862 is a current-output D/A converter. T herefore, an
external amplifier, in combination with the on-board feedback
resistor, is required to derive an output voltage. Figure 9 illus-
trates the proper connections for an external operational ampli-
fier. T he output of the AD1862 is intended to drive the
summing junction of an external current-to-voltage conversion
op amp. T herefore, the voltage on the output current pin of the
AD1862 should be approximately the same as that on the
AGND pin of the device.
T he ±VL supplies operate the digital portions of the chip includ-
ing the input shift register, the input latching circuitry and the
T T L-to-CMOS level shifters. T he ±VL supplies are designed to
be operated from ±5 V to ±12 V supplies subject only to the
limitation that –VL may not be more negative than –VS.
Decoupling capacitors should be used on all power supply input
pins. Good engineering practice suggests that these capacitors
be placed as close as possible to the package pins and the com-
mon points. T he logic supplies, ±VL, should be decoupled to
DGND and the analog supplies, ±VS, should be decoupled to
AGND.
T he on-board 3 kΩ feedback resistor and the ±1 mA output
current typically have ±1% tolerance or less. T his makes the
choice of external components very simple and eliminates addi-
tional trimming. For example, if a user wishes to derive an out-
put voltage higher than the ±3 V swing offered by the output
current and feedback resistor combination, all that is required is
to combine a standard value resistor with the feedback resistor
to achieve the appropriate output voltage swing. T his technique
can be extended to include the choice of elements in the
deemphasis network, etc.
EXTERNAL NO ISE RED UCTIO N CO MP O NENTS
Two external capacitors are required to achieve low-noise opera-
tion. Their correct connection is illustrated in Figure 8. Capacitor
C1 is connected between the pin labeled NR1 and analog com-
mon. C1 forms a low-pass filter element which reduces noise con-
–6–
REV. A
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