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AD1854JRSZRL PDF预览

AD1854JRSZRL

更新时间： 2024-01-12 11:07:57
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
12页 381K
描述
Stereo, 96 kHz, Multibit Sigma-Delta DAC

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AD1854JRSZRL 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：End Of Life零件包装代码：SSOP
包装说明：SSOP-28针数：28
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.57
最大模拟输出电压：2.8 V最小模拟输出电压：-2.8 V
转换器类型：D/A CONVERTER输入位码：2'S COMPLEMENT
输入格式：SERIALJESD-30 代码：R-PDSO-G28
JESD-609代码：e0长度：10.2 mm
湿度敏感等级：1位数：24
功能数量：2端子数量：28
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP28,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：240
电源：5 V认证状态：Not Qualified
座面最大高度：2 mm子类别：Other Converters
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：5.3 mm
Base Number Matches：1

AD1854JRSZRL 数据手册

 浏览型号AD1854JRSZRL的Datasheet PDF文件第2页浏览型号AD1854JRSZRL的Datasheet PDF文件第3页浏览型号AD1854JRSZRL的Datasheet PDF文件第4页浏览型号AD1854JRSZRL的Datasheet PDF文件第6页浏览型号AD1854JRSZRL的Datasheet PDF文件第7页浏览型号AD1854JRSZRL的Datasheet PDF文件第8页 
AD1854  
PIN FUNCTION DESCRIPTIONS  
Pin  
Input/Output  
Pin Name  
Description  
1
2
I
I
DGND  
MCLK  
Digital Ground.  
Master Clock Input. Connect to an external clock source at either 256, 384  
or 512 FS.  
3
4
I
I
CLATCH  
CCLK  
Latch input for control data. This input is rising-edge sensitive.  
Control clock input for control data. Control input data must be valid on the  
rising edge of CCLK. CCLK may be continuous or gated.  
5
6
I
I
CDATA  
Serial control input, MSB first, containing 16 bits of unsigned data per  
channel. Used for specifying channel-specific attenuation and mute.  
Selects the master clock mode as either 384 times the intended sample  
frequency (HI) or 256 times the intended sample frequency (LO). The state  
of this input should be hardwired to logic HI or logic LO, or may be changed  
while the AD1854 is in power-down/reset. It must not be changed while the  
AD1854 is operational.  
384/256  
7
8
I
O
X2MCLK  
ZEROR  
Selects internal clock doubler (LO) or internal clock = MCLK (HI).  
Right Channel Zero Flag Output. This pin goes HI when Right Channel has  
no signal input for more than 1024 LR Clock Cycles.  
9
I
DEEMP  
De-Emphasis. Digital de-emphasis is enabled when this input signal is HI.  
This is used to impose a 50 µs/15 µs response characteristic on the output  
audio spectrum at an assumed 44.1 kHz sample rate.  
10  
11, 15  
12  
13  
14  
I
I
O
O
O
96/48  
Selects 48 kHz (LO) or 96 kHz Sample Frequency Control.  
Analog Ground.  
Right Channel Positive line level analog output.  
Right Channel Negative line level analog output.  
AGND  
OUTR+  
OUTR–  
FILTR  
Voltage Reference Filter Capacitor Connection. Bypass and decouple the  
voltage reference with parallel 10 µF and 0.1 µF capacitors to the AGND.  
16  
17  
18  
19  
20  
O
O
I
O
I
OUTL–  
OUTL+  
AVDD  
FILTB  
IDPM1  
Left Channel Negative line level analog output.  
Left Channel Positive line level analog output.  
Analog Power Supply. Connect to analog 5 V supply.  
Filter Capacitor connection, connect 10 µF capacitor to AGND.  
Input serial data port mode control one. With IDPM0, defines one of four  
serial modes.  
21  
22  
23  
24  
I
IDPM0  
ZEROL  
MUTE  
PD/RST  
Input serial data port mode control zero. With IDPM1, defines one of four  
serial modes.  
Left Channel Zero Flag Output. This pin goes HI when Left Channel has no  
signal input for more than 1024 LR Clock Cycles.  
Mute. Assert HI to mute both stereo analog outputs. Deassert LO for nor-  
mal operation.  
Power-Down/Reset. The AD1854 is placed in a low power consumption  
mode when this pin is held LO. The AD1854 is reset on the rising edge of  
this signal. The serial control port registers are reset to the default values.  
Connect HI for normal operation.  
O
I
I
25  
26  
I
I
L/RCLK  
BCLK  
Left/Right clock input for input data. Must run continuously.  
Bit clock input for input data. Need not run continuously; may be gated or  
used in a burst fashion.  
27  
28  
I
I
SDATA  
DVDD  
Serial input, MSB first, containing two channels of 16, 18, 20, and 24 bits of  
twos complement data per channel.  
Digital Power Supply Connect to digital 5 V supply.  
REV. A  
–5–  
12345678...12

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