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AD1847JP PDF预览

AD1847JP

更新时间: 2024-02-03 11:34:41
品牌 Logo 应用领域
亚德诺 - ADI 解码器编解码器商用集成电路
页数 文件大小 规格书
28页 313K
描述
Serial-Port 16-Bit SoundPort Stereo Codec

AD1847JP 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:LCC
包装说明:PLASTIC, LCC-44针数:44
Reach Compliance Code:unknown风险等级:5.89
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:S-PQCC-J44
JESD-609代码:e0长度:16.585 mm
湿度敏感等级:NOT SPECIFIED功能数量:1
端子数量:44最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:COMMERCIAL座面最大高度:4.57 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:16.585 mm

AD1847JP 数据手册

 浏览型号AD1847JP的Datasheet PDF文件第4页浏览型号AD1847JP的Datasheet PDF文件第5页浏览型号AD1847JP的Datasheet PDF文件第6页浏览型号AD1847JP的Datasheet PDF文件第8页浏览型号AD1847JP的Datasheet PDF文件第9页浏览型号AD1847JP的Datasheet PDF文件第10页 
AD1847  
Miscellaneous  
P in Nam e  
P LCC  
TQFP  
I/O  
D escription  
XT AL1I  
XT AL1O  
XT AL2I  
XT AL2O  
XCT L1:O  
40  
41  
42  
43  
34  
35  
36  
37  
I
24.576 MHz Crystal # 1 Input.  
24.576 MHz Crystal # 1 Output.  
16.9344 MHz Crystal # 2 Input.  
16.9344 MHz Crystal # 2 Output.  
O
I
O
O
37 & 36 31 & 30  
External Control. T hese T T L signals reflect the current status of register bits inside the  
AD1847. T hey can be used for signaling or to control external logic.  
VREF  
16  
10  
O
Voltage Reference. Nominal 2.25 volt reference available externally as a voltage datum  
for dc-coupling and level-shifting. VREF should not have any signal dependent load.  
VREFI  
15  
21  
9
I
I
Voltage Reference Internal. Voltage reference filter point for external bypassing only.  
L_FILT  
15  
Left Channel Filter Capacitor. T his pin requires a 1.0 µF capacitor to analog ground  
for proper operation.  
R_FILT  
NC  
19  
29  
13  
23  
I
Right Channel Filter Capacitor. T his pin requires a 1.0 µF capacitor to analog ground  
for proper operation.  
No Connect. Do not connect.  
P ower Supplies  
P in Nam e  
P LCC  
TQFP  
I/O  
D escription  
VCC  
13 & 25  
7 & 19  
I
I
I
I
Analog Supply Voltage (+5 V).  
Analog Ground.  
GNDA  
VDD  
14, 20, 24  
2, 9, 34, 39  
3, 10, 35, 38  
8, 14, 18  
40, 3, 28, 33  
41, 4, 29, 32  
Digital Supply Voltage (+5 V).  
Digital Ground.  
GNDD  
(Continued from page 1)  
Analog Mixing  
AUX1 and AUX2 analog stereo signals can be mixed in the ana-  
log domain with the DAC output. Each channel of each auxil-  
iary analog input can be independently gained/attenuated from  
+12 dB to –34.5 dB in –1.5 dB steps or completely muted. T he  
post-mixed DAC output is available on L_OUT and R_OUT  
externally and as an input to the ADCs.  
T he ∑∆ DACs are preceded by a digital interpolation filter. An  
attenuator provides independent user volume control over each  
DAC channel. Nyquist images are removed from the DACs’  
analog stereo output by on-chip switched-capacitor and  
continuous-time filters. T wo stereo pairs of auxiliary line-level  
inputs can also be mixed in the analog domain with the DAC  
output.  
Even if the AD1847 is not playing back data from its DACs, the  
analog mix function can still be active.  
T he AD1847 serial data interface uses a T ime Division Multi-  
plex (T DM) scheme that is compatible with DSP serial ports  
configured in Multi-Channel Mode with 32 16-bit time slots  
(i.e., SPORT 0 on the ADSP-2101, ADSP-2115, etc.).  
Analog-to-D igital D atapath  
T he ∑∆ ADCs incorporate a proprietary fourth-order modula-  
tor. A single pole of passive filtering is all that is required for  
antialiasing the analog input because of the ADC’s high 64  
times oversampling ratio. T he ADCs include digital decimation  
filters that low-pass filter the input to 0.4 ϫ FS. (“FS’’ is the  
word rate or “sampling frequency.”) ADC input overrange con-  
ditions will cause status bits to be set that can be read.  
AUD IO FUNCTIO NAL D ESCRIP TIO N  
T his section overviews the functionality of the AD1847 and is  
intended as a general introduction to the capabilities of the de-  
vice. As much as possible, detailed reference information has  
been placed in “Control Registers” and other sections. T he user  
is not expected to refer repeatedly to this section.  
D igital-to-Analog D atapath  
T he ∑∆ DACs contain a programmable attenuator and a low-  
pass digital interpolation filter. T he anti-imaging interpolation  
filter oversamples and digitally filters the higher frequency im-  
ages. T he attenuator allows independent control of each DAC  
channel from 0 dB to –94.5 dB in 1.5 dB steps plus full mute.  
T he DACs∑∆ noise shapers also oversample and convert the  
signal to a single-bit stream. T he DAC outputs are then filtered  
in the analog domain by a combination of switched-capacitor  
and continuous-time filters. T hese filters remove the very high  
frequency components of the DAC bitstream output. No exter-  
nal components are required.  
Analog Inputs  
T he AD1847 SoundPort Stereo Codec accepts stereo line-level  
inputs. All inputs should be capacitively coupled (ac-coupled) to  
the AD1847. LINE1, LINE2, and AUX1, and post-mixed DAC  
output analog stereo signals are multiplexed to the internal pro-  
grammable gain amplifier (PGA) stage.  
T he PGA following the input multiplexer allows independent  
selectable gains for each channel from 0 to 22.5 dB in +1.5 dB  
steps. T he Codec can operate either in a global stereo mode or  
in a global mono mode with left-channel inputs appearing at  
both channel outputs.  
REV. B  
–7–  

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