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AD1845JP-REEL PDF预览

AD1845JP-REEL

更新时间: 2024-01-17 07:27:34
品牌 Logo 应用领域
亚德诺 - ADI 解码器编解码器
页数 文件大小 规格书
40页 335K
描述
Parallel-Port 16-Bit SoundPort Stereo Codec

AD1845JP-REEL 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:100
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
Is Samacsys:N商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-PQFP-G100JESD-609代码:e3
长度:14 mm湿度敏感等级:3
功能数量:1端子数量:100
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.45 mm最大压摆率:130 mA
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:14 mm
Base Number Matches:1

AD1845JP-REEL 数据手册

 浏览型号AD1845JP-REEL的Datasheet PDF文件第1页浏览型号AD1845JP-REEL的Datasheet PDF文件第2页浏览型号AD1845JP-REEL的Datasheet PDF文件第3页浏览型号AD1845JP-REEL的Datasheet PDF文件第5页浏览型号AD1845JP-REEL的Datasheet PDF文件第6页浏览型号AD1845JP-REEL的Datasheet PDF文件第7页 
AD1845  
SYSTEM SP ECIFICATIO NS  
Min  
Min  
Typ  
Max  
Units  
System Frequency Response Ripple (Line In to Line Out)*  
Differential Nonlinearity*  
Phase Linearity Deviation*  
1.0  
±1  
5
dB  
LSB  
Degrees  
STATIC D IGITAL SP ECIFICATIO NS  
Max  
Units  
High Level Input Voltage (VIH  
Digital Inputs  
XT AL1I  
)
2.4  
2.4  
V
V
Low Level Input Voltage (VIL)  
0.8  
V
High Level Output Voltage (VOH ) IOH = –2 mA  
Low Level Output Voltage (VOL) IOL = 2 mA  
Input Leakage Current  
2.4  
V
V
µA  
µA  
0.4  
10  
10  
–10  
–10  
Output Leakage Current  
TIMING P ARAMETERS (GUARANTEED O VER O P ERATING TEMP ERATURE RANGE, VD D = VCC = 5.0 V)  
Min  
Max  
Units  
WR/RD Strobe Width  
(tST W  
(tBWND  
(tWDSU  
)
100  
80  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WR/RD Rising to WR/RD Falling  
Write Data Setup to WR  Rising  
RD Falling to Valid Read Data  
CS Setup to WR/RD Falling  
CS Hold from WR/RD Rising  
Adr Setup to WR/RD Falling  
Adr Hold from WR/RD Rising  
DAK Rising to WR/RD Falling  
DAK Falling to WR/RD Rising  
DAK Setup to WR/RD Falling  
Data Hold from RD Rising  
Data Hold from WR Rising  
DRQ Hold from WR/RD Falling  
DAK Hold from WR Rising  
DAK Hold from RD Rising  
)
)
)
(tRDDV  
40  
(tCSSU  
(tCSHD  
(tADSU  
(tADHD  
(tSUDK1  
(tSUDK2  
(tDKSU  
(tDHD1  
(tDHD2  
(tDRHD  
(tDKHDa  
(tDKHDb  
)
10  
0
10  
10  
20  
0
)
)
)
)
)
)
)
)
10  
20  
25  
15  
)
)
)
10  
10  
DBEN/ DBDIR Delay from WR/ RD Falling (tDBDL  
PWRDWN and RESET Low Pulsewidth  
)
30  
300  
*Guaranteed, not tested.  
REV. C  
–4–  

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