AD1555BPRL

更新时间： 2024-01-17 19:59:14

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	419K
描述
24-Bit ADC WITH LOW NOISE PGA

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数据手册

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AD1555BPRL 数据手册

AD1555/AD1556

TIMING SPECIFICATIONS ⁽^C⁺^L^V^KIN⁼⁼⁺¹⁵^.0^V²^ꢂ^{4 M}⁵^H^%^z^;^;^–^AGVN⁼^{D =}^–5^D^V^GN^ꢂ^D⁵⁼^%⁰^;^V^A;D^C¹_L⁵⁼⁵⁵⁵^V^{0 p}⁼^F;5T^V_A⁼^ꢂ^T⁵_MI^%_Nt^,o^ADT_M¹_A⁵_X⁵, ⁶un^Vles⁼s²o^.t⁸h⁵er^Vw^ti^ose^5.n²o⁵te^Vd^;)

Symbol

Min

Typ

Max

Unit

CLKIN Frequency¹

f_CLKIN

0.975

1.024

1.075

MHz

CLKIN Duty Cycle Error

MCLK Output Frequency¹

f_CLKIN/4

SYNC Setup Time

SYNC Hold Time

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

t₉

CLKIN Rising to MCLK Output Falling on SYNC

CLKIN Falling to MCLK Output Rising

CLKIN Falling to MCLK Output Falling

MCLK Input Falling to MDATA Falling

MCLK Input Rising to MDATA and MFLG Valid

TDATA Setup Time after SYNC

TDATA Hold Time

100

RESET Setup Time

RESET Hold Time

t₁₀

t₁₁

CLKIN Falling to DRDY Rising

CLKIN Rising to DRDY Falling²

CLKIN Rising to ERROR Falling

t₁₂

t₁₃

t₁₄

RSEL to Data Valid

RSEL Setup to SCLK Falling

DRDY to Data Valid

DRDY High Setup to SCLK Falling

R/W to Data Valid

R/W High Setup to SCLK Falling

CS to Data Valid

CS Low Setup to SCLK Falling

SCLK Rising to DOUT Valid

SCLK High Pulsewidth

t₁₅

t₁₆

t₁₇

t₁₈

t₁₉

t₂₀

t₂₁

t₂₂

t₂₃

t₂₄

t₂₅

t₂₆

t₂₇

t₂₈

SCLK Low Pulsewidth

SCLK Period

SCLK Falling to DRDY Falling²

CS High or R/W Low to DOUT Hi-Z

R/W Low Setup to SCLK Falling

CS Low Setup to SCLK Falling

Data Setup Time to SCLK Falling

Data Hold Time after SCLK Falling

R/W Hold Time after SCLK Falling

t₂₉

t₃₀

t₃₁

t₃₂

t₃₃

NOTES

¹The gain of the modulator is proportional to f_CLKINand MCLK frequency.

²With DRDYBUF low only. When DRDYBUF is high, this timing also depends on the value of the external pull-down resistor.

Specifications subject to change without notice.

1.6mA

TO OUTPUT

1.4V

50pF

500ꢃA

Figure 2. Load Circuit for Digital Interface Timing

–5–

REV. B

1 2 3 456 7 8...24

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