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AD10465PCB

更新时间： 2024-01-17 08:14:37
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
20页 2425K
描述
Dual Channel, 14-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning

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AD10465PCB 技术参数

Source Url Status Check Date：2013-05-01 14:56:08.131是否无铅：含铅
是否Rohs认证：不符合生命周期：Active
零件包装代码：QFP包装说明：QFP, LDCC68,1.0SQ
针数：68Reach Compliance Code：not_compliant
ECCN代码：3A991.C.3HTS代码：8542.39.00.01
风险等级：5.64Is Samacsys：N
最大模拟输入电压：2 V最小模拟输入电压：-2 V
转换器类型：ADC, PROPRIETARY METHODJESD-30 代码：S-CQFP-G68
长度：24.13 mm标称负供电电压：-5 V
模拟输入通道数量：3位数：14
功能数量：2端子数量：68
最高工作温度：85 °C最低工作温度：-40 °C
输出位码：2'S COMPLEMENT BINARY输出格式：PARALLEL, WORD
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QFP
封装等效代码：LDCC68,1.0SQ封装形状：SQUARE
封装形式：FLATPACK峰值回流温度（摄氏度）：220
电源：3.3,5 V认证状态：Not Qualified
采样速率：65 MHz采样并保持/跟踪并保持：TRACK
座面最大高度：4.45 mm子类别：Analog to Digital Converters
标称供电电压：5 V表面贴装：YES
技术：BIPOLAR温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：24.13 mmBase Number Matches：1

AD10465PCB 数据手册

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AD10465  
Test  
Mil  
AD10465AZ/BZ/QML-H  
Parameter  
Temp  
Level  
Subgroup Min  
Typ  
Max  
Unit  
SPURIOUS-FREE DYNAMIC RANGE8  
Analog Input @ 4.98 MHz  
Analog Input @ 9.9 MHz  
25°C  
25°C  
Full  
25°C  
Full  
V
I
II  
I
II  
I
II  
85  
82  
82  
78  
78  
68  
66  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
4
5, 6  
4
5, 6  
4
5, 6  
73  
70  
72  
70  
62  
60  
Analog Input @ 19.5 MHz  
Analog Input @ 32.1 MHz  
25°C  
Full  
TWO-TONE IMD REJECTION9  
fIN = 10 MHz and 11 MHz  
f1 and f2 are –7 dB  
25°C  
I
II  
I
4
5, 6  
4
78  
78  
68  
60  
87  
70  
dBFS  
dBFS  
f
IN = 31 MHz and 32 MHz  
25°C  
Full  
f1 and f2 Are –7 dB  
II  
5, 6  
CHANNEL-TO-CHANNEL ISOLATION10  
25°C  
25°C  
IV  
V
12  
90  
dB  
ns  
TRANSIENT RESPONSE  
15.3  
OVERVOLTAGE RECOVERY TIME11  
VIN = 2.0 × fS  
VIN = 4.0 × fS  
Full  
Full  
IV  
IV  
12  
12  
40  
150  
100  
200  
ns  
ns  
DIGITAL OUTPUTS12  
Logic Compatibility  
DVCC = 3.3 V  
CMOS  
Logic “1” Voltage  
Logic “0” Voltage  
DVCC = 5 V  
Full  
Full  
I
I
1, 2, 3  
1, 2, 3  
2.5  
DVCC – 0.2  
0.2  
V
V
0.5  
Logic “1” Voltage  
Logic “0” Voltage  
Output Coding  
Full  
Full  
V
V
DVCC – 0.3  
0.35  
Two’s Complement  
V
V
POWER SUPPLY  
AVCC Supply Voltage13  
I (AVCC) Current  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
VI  
I
4.85  
5.0  
270  
–5.0  
38  
3.3  
30  
338  
3.5  
0.02  
0.1  
0.2  
5.25  
308  
–4.75  
49  
3.465  
46  
V
mA  
V
mA  
V
mA  
mA  
W
AVEE Supply Voltage13  
I (AVEE) Current  
VI  
V
VI  
V
I
–5.25  
3.135  
DVCC Supply Voltage13  
I (DVCC) Current  
I
CC (Total) Supply Current per Channel  
1, 2, 3  
1, 2, 3  
403  
3.9  
Power Dissipation (Total)  
I
Power Supply Rejection Ratio (PSRR)  
Passband Ripple to 10 MHz  
Passband Ripple to 25 MHz  
V
V
V
% FSR/% VS  
dB  
dB  
NOTES  
1 Gain tests are performed on AIN1 input voltage range.  
2 Input Capacitance spec. combines AD8037 die capacitance and ceramic package capacitance.  
3 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.  
4 All ac specifications tested by driving ENCODE and ENCODE differentially.  
5 Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% 5%.  
6 Analog input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 65 MSPS. SNR  
is reported in dBFS, related back to converter full power.  
7 Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS.  
8 Analog input signal power swept from –1 dBFS to –60 dBFS; SFDR is ratio of converter full scale to worst spur.  
9 Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product.  
10 Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel.  
11 Input driven to 2× and 4× AIN1 range for > four clock cycles. Output recovers inband in specified time with Encode = 65 MSPS.  
12 Digital output logic levels: DVCC = 3.3 V, CLOAD = 10 pF. Capacitive loads > 10 pF will degrade performance.  
13 Supply voltage recommended operating range. AVCC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range  
AVCC = 5.0 V to 5.25 V.  
All specifications guaranteed within 100 ms of initial power-up regardless of sequencing.  
Specifications subject to change without notice.  
–3–  
REV. 0  
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