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ACS761ELFTR-20B-T

更新时间： 2024-02-17 04:32:29
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急速微 - ALLEGRO 模拟IC信号电路光电二极管监控
页数 文件大小 规格书
14页 375K
描述
12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC

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ACS761ELFTR-20B-T 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP, SSOP24,.24针数：24
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.81模拟集成电路 - 其他类型：ANALOG CIRCUIT
JESD-30 代码：R-PDSO-G24JESD-609代码：e3
长度：8.66 mm湿度敏感等级：2
功能数量：1端子数量：24
最高工作温度：85 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP24,.24封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：12 V认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Power Management Circuits
最大供电电流 (Isup)：10.5 mA最大供电电压 (Vsup)：13.2 V
最小供电电压 (Vsup)：10.8 V标称供电电压 (Vsup)：12 V
表面贴装：YES温度等级：OTHER
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.91 mm
Base Number Matches：1

ACS761ELFTR-20B-T 数据手册

 浏览型号ACS761ELFTR-20B-T的Datasheet PDF文件第4页浏览型号ACS761ELFTR-20B-T的Datasheet PDF文件第5页浏览型号ACS761ELFTR-20B-T的Datasheet PDF文件第6页浏览型号ACS761ELFTR-20B-T的Datasheet PDF文件第8页浏览型号ACS761ELFTR-20B-T的Datasheet PDF文件第9页浏览型号ACS761ELFTR-20B-T的Datasheet PDF文件第10页 
ACS761ELF-20B  
12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC  
OPERATING CHARACTERISTICS (continued) valid at VCC = 12 V, TA = 0°C to 85°C, unless otherwise noted  
Characteristic  
Symbol  
Test Conditions  
Min.  
Typ.  
Max.  
Units  
Gate Drive Performance Characteristics  
Nominal Gate Voltage  
VGATE  
TA = 25°C  
–
–
VCC +10  
–
±2  
70  
–
V
V
Gate Voltage Tolerance  
ΔVGATE  
IGD  
TA = 25°C  
–
50  
1
Average GATE Drive Current  
Charge Pump Switching Frequency  
VCC = 12 V, TA = 25°C  
TA = 25°C  
30  
–
ꢁA  
MHz  
fCP  
TA = 25°C, external MOSFET S1 gate capacitance = 5.8 nF,  
measured from VGATE = 0 to 15 V, CG pin open, no output  
load capacitance  
GATE Rise Time  
tGR  
–
1
–
ms  
GATE Sink Resistance7  
RGsink  
< 5 μs after gate voltage falls low  
–
–
–
20  
30  
–
Ω
kΩ  
ns  
GATE Sink Steady State  
Resistance7  
RGsink(ss) > 80 μs after gate voltage falls low  
tGSD Measured from fault event to start of GATE pull down  
100  
200  
GATE Shutdown Delay  
GATE Maximum Fall Time  
CG Output Current  
–
Measured from VGATE = 90% of maximum to VGATE < 1 V,  
while EN pin switched from high to low, assuming external  
MOSFET S1 gate capacitance = 5.8 nF  
tGF  
–
800  
20  
–
ns  
ISLEW  
TA = 25°C  
18  
22  
μA  
1 The small signal, ac bandwidth of this device is approximately 90 kHz.  
2 This is the 6 σ noise voltage.  
3 This test requires currents sufficient to swing the output driver between the fully off state and the saturated state. Assumes that the VIOUT pin is con-  
nected to an analog-to-digital converter that saturates at 2.5 V. The VIOUT signal is linear above 2.5 V, however, this test is NOT intended to indicate a  
range of linear operation.  
4 This is the minimum delay time achievable without COPD or COCD. Longer delay time can be achieved by using COPD or COCD. See Functional  
Description section for details. Voltage trip point for both the OPDLY and the OCDLY pins is 3.85 V.  
5 This parameter is internally programmed and cannot be controlled by the end user.  
6 The FAULT output signal is latched. After a latched fault event, the device will be reset only when either: (a) VEN drops below VENL, or (b) the power to  
the device (applied to the IP+ pins) is toggled off and then back on.  
7 The gate resistance switches to high impedance approximately 15 to 45 μs after the gate voltage falls low after a fault.  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
7
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  
1...45678910...14

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