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ACS374K/SAMPLE

更新时间： 2024-01-21 08:34:15
品牌 Logo 应用领域
瑞萨 - RENESAS 驱动输出元件逻辑集成电路
页数 文件大小 规格书
8页 73K
描述
AC SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDFP20, CERAMIC, DFP-20

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ACS374K/SAMPLE 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.04系列：AC
JESD-30 代码：R-CDFP-F20逻辑集成电路类型：BUS DRIVER
位数：8功能数量：1
端口数量：2端子数量：20
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
传播延迟（tpd）：16 ns认证状态：Not Qualified
座面最大高度：2.92 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL宽度：6.92 mm
Base Number Matches：1

ACS374K/SAMPLE 数据手册

 浏览型号ACS374K/SAMPLE的Datasheet PDF文件第2页浏览型号ACS374K/SAMPLE的Datasheet PDF文件第3页浏览型号ACS374K/SAMPLE的Datasheet PDF文件第4页浏览型号ACS374K/SAMPLE的Datasheet PDF文件第5页浏览型号ACS374K/SAMPLE的Datasheet PDF文件第6页浏览型号ACS374K/SAMPLE的Datasheet PDF文件第7页 
ACS374MS  
Radiation Hardened  
Octal D Flip-Flop, Three-State  
April 1995  
Features  
• 1.25 Micron Radiation Hardened SOS CMOS  
Pinouts  
20 LEAD CERAMIC DUAL-IN-LINE  
MIL-STD-1835 DESIGNATOR CDIP2-T20, LEAD FINISH C  
TOP VIEW  
• Total Dose 300K RAD (Si)  
• Single Event Upset (SEU) Immunity  
<1 x 10-10 Errors/Bit-Day (Typ)  
• SEU LET Threshold >80 MEV-cm2/mg  
1
2
3
4
5
6
7
8
9
VCC  
Q7  
OE  
Q0  
D0  
D1  
Q1  
Q2  
D2  
D3  
Q3  
20  
19  
18 D7  
17 D6  
16 Q6  
15 Q5  
14 D5  
13 D4  
• Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse  
• Latch-Up Free Under Any Conditions  
• Military Temperature Range: -55oC to +125oC  
• Significant Power Reduction Compared to ALSTTL Logic  
• DC Operating Voltage Range: 4.5V to 5.5V  
12  
Q4  
• Input Logic Levels  
GND 10  
11 CP  
- VIL = 30% of VCC Max  
- VIH = 70% of VCC Min  
20 LEAD CERAMIC FLATPACK  
MIL-STD-1835 DESIGNATOR CDFP4-F20, LEAD FINISH C  
TOP VIEW  
• Input Current ≤1µA at VOL, VOH  
OE  
Q0  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
Q7  
D7  
D6  
Q6  
Q5  
D5  
D4  
Q4  
CP  
Description  
The Intersil ACS374MS is a radiation hardened octal D-type flip-  
flop with three-state outputs. The eight edge-triggered flip-flops  
enter data into their registers on the low to high transition of clock  
(CP). The Output Enable (OEN) controls the three-state outputs  
and is independent of the register operation. When the OEN is  
high, the outputs will be in the high impedance state.  
D0  
D1  
Q1  
Q2  
D2  
D3  
The ACS374MS utilizes advanced CMOS/SOS technology to  
achieve high-speed operation. This device is a member of the  
radiation hardened, high-speed, CMOS/SOS Logic Family.  
Q3  
GND  
Ordering Information  
PART NUMBER  
ACS374DMSR  
TEMPERATURE RANGE  
SCREENING LEVEL  
Intersil Class S Equivalent  
Intersil Class S Equivalent  
Sample  
PACKAGE  
o
o
-55 C to +125 C  
20 Lead SBDIP  
o
o
ACS374KMSR  
-55 C to +125 C  
20 Lead Ceramic Flatpack  
20 Lead SBDIP  
o
ACS374D/Sample  
ACS374K/Sample  
ACS374HMSR  
+25 C  
o
+25 C  
Sample  
20 Lead Ceramic Flatpack  
Die  
o
+25 C  
Die  
Truth Table  
Functional Diagram  
1 OF 8  
INPUTS  
CP  
OUTPUTS  
FF  
OE  
L
Dn  
H
L
Qn  
H
D
Q
D
Q
CP  
OE  
L
L
COMMON CONTROLS  
CP  
L
X
X
X
Q0  
Z
H
X
H = High Level  
L = Low Level  
X = Immaterial  
Z = High Impedance  
= Transition from Low to High Level  
Q0  
= the level of Q before the indicated input conditions  
were established  
OE  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518820  
File Number 3997  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
1
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