Advanced Communications
ACS102A Data Sheet
Using drift lock, synchronisation described above depends on a
difference in the XTAL frequencies at each end of the link, and the
greater the difference the faster the locking. Therefore, if the
difference between XTAL frequencies is very small (a few ppm),
automatic locking may take tens of seconds or even minutes.
crystal oscillator will operate with padding capacitors of value 0 -50pF,
and the designer should endeavour to use padding capacitors of low
value since this will ensure the lowest power consumption. The
ACS102A has been designed to operate with a crystal tolerance of +/
- 250ppm giving a relative tolerance between communicating modem
pairs of 500ppm. This wide tolerance will support the use of low value
padding capacitors.
Drift lock will not operate if the two communicating devices are driven by
a clock derived from a single source (i.e. tolerance of 0ppm).
Alternatively, XLI may be driven directly by an external clock. The
clock frequency for the purpose of this specification is referred to as
the XTAL frequency. The operational range for the XTAL frequency is
5 - 27MHz, though communicating devices must use the same
nominal value.
Active Lock Mode
Active lock mode may be used to accelerate synchronisation of a
pair of communicating modems. This mode synchronises the
modems in less than 3 seconds by adjusting the machine cycles of
the modems. Active lock reduces the machine cycle of the device
by 0.5 % ensuring rapid lock. After synchronisation the machine
cycle reverts automatically to normal.
DCDB
The Data Carrier Detect (DCDB) signal goes Low when the modems
are synchronised ('locked') and ready for data transmission. Prior to
lock (DCDB = High), the data channel output RxD will be forced Low
and the handshake outputs CTS and DSR will be forced High.
Only one device may be configured in active lock mode at any one
time. Active lock mode is usually invoked temporarily on power-up.
This can be achieved on the ACS102A by connecting DM1 to an RC
arrangement, i.e. with the capacitor to 5V and the resistor to GND, to
create a 5V à 0V ramp on power-up. The RC time constant should
be Ca. 5 seconds. Active lock will succeed even when
communicating devices are driven from clocks derived from a single
source (0ppm).
The status of DCDB is also given by the HBT pin. See section headed
HBT Status pin.
CNT Capacitor
The CNT value is inversely proportional to the XTAL frequency. The
capacitor is connected between pins CNT and GND.
A
20 %
Random Lock
tolerance on CNT is sufficient. For a XTAL frequency range of
5 to 27MHz the recommended value of the capacitor on CNT is from
47nF at 5MHz, 22nF at 10MHz down to 10nF at 27MHz . A ceramic
type is required to ensure low leakage. The CNT capacitor value has
an effect on the initial locking time and the receiver sensitivity limit.
Higher values giving improved sensitivity and lower values giving
faster locking.
This mode achieves moderate locking times (typically 5 seconds,
worst case 10 seconds) with the advantage that the ACS102’s are
configured as peers. Communicating modems may be permanently
configured in this mode by hard wiring the DM pins.
2
Random lock will succeed even when communicating devices are
driven from clocks derived from a single source (0ppm). Random
lock mode is compatible with drift lock and active lock.
ERL (Error Detector)
Memory Lock
This signal can be used to give an indication of the quality of the
optical link. Even when a DC signal is applied to the data and
handshake inputs, the ACS102A modem transmits up to 200kbps
over the link in each direction. This control data is used to maintain
the timing and the relative positioning of 'transmit' and 'receive'
windows.
Following the assertion of a reset (PORB = 0) communicating
devices will initiate an arbitration process where within 10 seconds
the communicating modems will achieve synchronisation with one
establishing itself as an active lock modem and the other
establishing itself as a drift lock modem. On subsequent attempts to
lock, synchronisation will be achieved within 3 seconds. It is only
necessary to apply reset to one device in the communicating pair to
initiate an arbitration process.
The transmit and control data is constantly monitored to make sure it
is compatible with the 3B4B format. If a coding error is detected, ERL
will go High and will remain High until reset. ERL may be reset by
asserting PORB, or by removing the fiber-optic cable from one side of
the link thereby forcing the device temporarily out of lock.
Since memory lock uses on-chip storage, loss of power to the
modem will require a new reset (PORB=0). Furthermore, should
there be a need to synchronise with a third modem a reset will again
be required.
Please note that ERL detects coding errors and not data errors,
nevertheless because of the complexity of the coding rules on the
ACS102A the absence of detected errors on this pin will give a good
indication of a high quality link.
Mixing Lock modes
It is possible to mix all combinations of locking modes once the
modems are locked, however, prior to synchronisation two modems
configured in active lock will not operate. The effect of mixing
locking modes on locking speed is given in Table 4 :
HBT Status pin ('Heartbeat' Indicator LED)
The ACS102A HBT pin affords a method of driving a display LED in a
manner which is sympathetic to low power consumption. The HBT pin
is pulsed to indicate 'locked' status (DCDB = 0) and 'out of lock' status
(DCDB =1). The frequency of pulses is 8 times greater for 'out of lock'
than for 'lock'. The LED 'on' indicates power-up whilst the frequency
of pulsing denotes locking status.
Device A
Mode
Device B
Mode
Locking Speed
Drift
Drift
Drift
Drift
Active
Active
Active
Random
Random
Memory
Drift
Active
Drift
Active
Random
Random
Not allowed
Random
Random
Random
Random
Memory
Active
Random
Memory
Random
Memory
Memory
Since the display LED is on for (at most) 3.2 % of the total time, the
HBT requires little power which may be further reduced by employing
high efficiency LEDs.
Powered-up, but not locked
Random
Active (Random on first synchronisation)
Frequency (Hz):
Duration (s):
On time (%):
XTAL / 3.89 * 106
61,440 / XTAL
3.2 % of time.
Frequency:
Table 4. Mixing lock modes
PORB
With 10MHz XTAL :
2.5Hz (approx.)
6.1ms (approx.)
Duration:
The Power-On Reset or PORB resets the device if forced Low for
100ms or more. This pin should be connected as figure 4.
Powered-up and locked
Frequency (Hz):
Duration (s):
On time (%):
XTAL / 15.36 * 106
Crystal Clock
61,440 / XTAL
0.4 % of time.
Frequency:
Duration:
Normally, a parallel resonant crystal will be connected between the
pins XLI and XLO with the appropriate padding capacitors. The
With 10MHz XTAL :
0.65Hz (approx.)
6.1 ms (approx.)
5
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