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ACS102-5TX PDF预览

ACS102-5TX

更新时间: 2024-02-16 17:00:16
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 开关
页数 文件大小 规格书
8页 98K
描述
AC LINE SWITCH

ACS102-5TX 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TO-92包装说明:PACKAGE-3
针数:3Reach Compliance Code:not_compliant
HTS代码:8541.30.00.80风险等级:5.8
其他特性:WITH BUILT IN CLAMPING STRUCTURE AND GATE LEVEL SHIFTER DRIVER配置:SINGLE WITH BUILT-IN TRIGGER ELEMENT IN SERIES WITH GATE
JEDEC-95代码:TO-92JESD-30 代码:O-PBCY-T3
JESD-609代码:e3元件数量:1
端子数量:3封装主体材料:PLASTIC/EPOXY
封装形状:ROUND封装形式:CYLINDRICAL
峰值回流温度(摄氏度):250认证状态:Not Qualified
最大均方根通态电流:0.2 A断态重复峰值电压:500 V
表面贴装:NO端子面层:Matte Tin (Sn)
端子形式:THROUGH-HOLE端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED触发设备类型:SNUBBERLESS TRIAC
Base Number Matches:1

ACS102-5TX 数据手册

 浏览型号ACS102-5TX的Datasheet PDF文件第2页浏览型号ACS102-5TX的Datasheet PDF文件第3页浏览型号ACS102-5TX的Datasheet PDF文件第4页浏览型号ACS102-5TX的Datasheet PDF文件第6页浏览型号ACS102-5TX的Datasheet PDF文件第7页浏览型号ACS102-5TX的Datasheet PDF文件第8页 
ACS102-5Tx  
AC LINE TRANSIENT VOLTAGE RUGGEDNESS  
The ACS102 switch is able to sustain safely the AC line transient voltages either by clamping the low en-  
ergy spikes or by breaking over under high energy shocks, even with high turn-on current rates of increase.  
The test circuit of the figure 3 is representative of the final ACS application and is also used to stress the  
ACS switch according to the IEC1000-4-5 standard conditions. Thanks to the load, the ACS switch sus-  
tains the voltage spikes up to 2 kV above the peak line voltage. It will breaks over safely even on resistive  
load where the turn on current rate of increase is high as shown on figure 4. Such non repetitive test can be  
done 10 times on each AC line voltage polarity.  
Fig. 3: Overvoltage ruggedness test circuit for  
resistive and inductive loads according to  
IEC 1000-4-5 standard.  
Fig. 4: Current and Voltage of the ACS during  
IEC 1000-4-5 standard test with R = 150, L =  
5µH & VPP = 2kV.  
R = 150, L = 5µH, VPP = 2kV.  
R
L
Vout (200 V/div)  
Iout (2.5 A/div)  
OUT  
AC LINE &  
SURGE VOLTAGE  
GENERATOR  
ACSxx  
S
V
AC + VPP  
ON  
D
COM  
G
dI/dt = 70 A/µs  
RG= 220  
Fig 5: Relative variation of gate trigger current  
versus junction temperature  
Fig 6: Relative variation of holding & latching  
currents versus junction temperature  
IH[Tj]/IH[Tj=25°C] & IL[Tj]/IL[Tj=25°C]  
IGT[Tj]/IGT[Tj=25°C]  
2.0  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
2.00  
1.75  
1.50  
1.25  
1.00  
0.75  
0.50  
0.25  
Tj(°C)  
0.2  
Tj(°C)  
0.00  
0.0  
0
25  
50  
75  
100  
125  
0
25  
50  
75  
100  
125  
5/8  

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