4.6.1 Graphics Register Ranges........................................................................ 54
4.6.1.1 VGA and Extended VGA Control Registers (0000_0000h to
0000_0FFFh)............................................................................ 54
4.6.1.2 Instruction, Memory, and Interrupt Control Registers (0000_1000h
to 0000_2FFFh)........................................................................ 54
4.6.2 I/O Mapped Access to Device 2 MMIO Space.............................................. 54
System Management Mode (SMM)....................................................................... 56
4.7.1 SMM Space Definition ............................................................................. 56
SMM Space Restrictions ..................................................................................... 57
4.8.1 SMM Space Combinations........................................................................ 57
4.8.2 SMM Control Combinations ...................................................................... 57
4.8.3 SMM Space Decode and Transaction Handling ............................................ 58
4.8.4 Processor WB Transaction to an Enabled SMM Address Space....................... 58
Memory Shadowing ........................................................................................... 58
4.7
4.8
4.9
4.10 I/O Address Space............................................................................................. 58
4.10.1 PCI Express I/O Address Mapping............................................................. 59
4.11 GMCH Decode Rules and Cross-Bridge Address Mapping......................................... 60
4.11.1 Legacy VGA and I/O Range Decode Rules.................................................. 60
5
System Memory Controller ...................................................................................... 61
5.1
5.2
Functional Overview .......................................................................................... 61
Memory Channel Access Modes ........................................................................... 62
5.2.1 Dual-Channel Interleaved Mode................................................................ 62
5.2.1.1 Intel Flex Memory Technology (Dual-Channel Interleaved Mode
with Unequal Memory Population) ............................................... 62
5.2.2 Dual-Channel Asymmetric Mode............................................................... 63
DRAM Technologies and Organization................................................................... 64
5.3.1 Rules for Populating SO-DIMM Slots.......................................................... 65
5.3.1.1 Single-Channel Population Rules for Systems with Intel
5.3
Management Engine Enabled...................................................... 65
5.3.2 Pin Connectivity for Dual-Channel Modes................................................... 65
DRAM Clock Generation...................................................................................... 66
DDR2/DDR3 On Die Termination ......................................................................... 66
DRAM Power Management.................................................................................. 66
5.6.1 Self Refresh Entry and Exit Operation........................................................ 66
5.6.2 Dynamic-Power-Down Operation .............................................................. 67
5.6.3 DRAM I/O Power Management ................................................................. 67
System Memory Throttling.................................................................................. 67
5.4
5.5
5.6
5.7
6
7
PCI Express-Based External Graphics ...................................................................... 68
6.1
6.2
PCI Express Configuration Mechanism.................................................................. 68
Concurrent Operation of Digital DisplayPorts Multiplexed with the GMCH PCI Express
Interface.......................................................................................................... 69
6.2.1 SDVO Multiplexed on the PCI Express Interface.......................................... 69
6.2.1.1 SDVO Signal Mapping................................................................ 71
6.2.2 Integrated HDMI/DVI (iHDMI) Multiplexed on the PCI Express Interface ........ 72
Co-Existence of DisplayPorts............................................................................... 74
6.3
Integrated Graphics Controller ................................................................................ 75
7.1
Gen 5.0 3D and Video Engines for Graphics Processing........................................... 75
7.1.1 3D Engine Execution Units (EUs) .............................................................. 76
7.1.2 3D Pipeline............................................................................................ 76
7.1.2.1 Vertex Fetch (VF) Stage............................................................. 76
7.1.2.2 Vertex Shader (VS) Stage.......................................................... 76
7.1.2.3 Geometry Shader Stage............................................................. 76
7.1.2.4 Clip Stage................................................................................ 76
7.1.2.5 Strips and Fans Stage ............................................................... 76
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