Datasheet > AAT2500IWP-AW-T1

AAT2500IWP-AW-T1

更新时间： 2024-02-13 21:34:41

品牌	Logo	应用领域
ANALOGICTECH		转换器稳压器
页数	文件大小	规格书
26页	862K
描述
1MHz Step-Down Converter/LDO Regulator

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技术参数
数据手册

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AAT2500IWP-AW-T1 技术参数

生命周期：	Transferred	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.69
Base Number Matches：	1

AAT2500IWP-AW-T1 数据手册

AAT2500

1MHz Step-Down Converter/LDO Regulator

Pin Descriptions

Pin #

Symbol

Function

PGND

Step-down converter power ground return pin. Connect to the output and input capaci-

tor return. See section on PCB layout guidelines and evaluation board layout diagram.

Power switching node. Output switching node that connects to the output inductor.

Step-down converter power stage supply voltage. Must be closely decoupled to PGND.

Step-down converter bias supply. Connect to VP.

VCC

VLDO

OUT

LDO input voltage; should be decoupled with 1µF or greater capacitor.

300mA LDO output pin. A 2.2µF or greater output low-ESR ceramic capacitor is

required for stability.

BYP

Bypass capacitor for the LDO. To improve AC ripple rejection, connect a 10nF capaci-

tor to GND. This will also provide a soft-start function.

GND

LDO ground connection pin.

ENLDO

Enable pin for LDO. When connected low, LDO is disabled and consumes less than

1µA of current.

Step-down converter enable. When connected low, LDO is disabled and consumes

less than 1µA.

Step-down converter feedback input pin. For fixed output voltage versions, this pin is

connected to the converter output, forcing the converter to regulate to the specific volt-

age. For adjustable output versions, an external resistive divider ties to this point and

programs the output voltage to the desired value.

SGND

Step-down converter signal ground. For external feedback, return the feedback resis-

tive divider to this ground. For internal fixed version, tie to the point of load return. See

section on PCB layout guidelines and evaluation board layout diagram.

Exposed paddle (bottom). Use properly sized vias for thermal coupling to the ground

plane. See section on PCB layout guidelines.

Pin Configuration

TDFN/STDFN33-12

(TopView)

PGND

VCC

VLDO

OUT

SGND

ENLDO

GND

BYP

2500.2006.05.1.16

123 4 5 6 7...26

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