AAA1337NXX
<Figure 30. HDR Output Timing>................................................................................................................49
<Figure 30. Module Schematic>.................................................................................................................60
<Figure 31. Spectral Response> ................................................................................................................61
Table Contents
[Table 1. DC Characteristics].......................................................................................................................10
[Table 2. Temperature Characteristics] .......................................................................................................10
[Table 3. Absolute Maximum Ratings].........................................................................................................10
[Table 4. Power Consumption] .................................................................................................................... 11
[Table 5. Master Clock Characteristics].......................................................................................................12
[Table 6. HS Transmitter DC Specifications]...............................................................................................13
[Table 7. HS Transmitter AC Specifications] ...............................................................................................13
[Table 8. LP Transmitter DC Specifications]................................................................................................13
[Table 9. LP Transmitter AC Specifications]................................................................................................13
[Table 10. AC Characteristics of Two Wire Serial Bus : Fast-mode]...........................................................14
[Table 11. AC Characteristics of Two Wire Serial Bus : Fast-mode Plus]...................................................15
[Table 12. Slave address setting]................................................................................................................15
[Table 13. Operation Mode Summary] ........................................................................................................21
[Table 14. Timing of Power Sequence] .......................................................................................................23
[Table 15. Analog Gain Register].................................................................................................................25
[Table 16. Analog Gain Setting]...................................................................................................................25
[Table 17. Integration Time Register] ..........................................................................................................26
[Table 18. LSC Register] .............................................................................................................................27
[Table 19. PD-LSC Operation Mode] ..........................................................................................................28
[Table 20. DPC Register].............................................................................................................................28
[Table 21. PD-DPC Operation Mode]..........................................................................................................28
[Table 22. Digital Gain Register]..................................................................................................................29
[Table 23. Subsampling and Binning Register]...........................................................................................30
[Table 24. Horizontal Scaling Register].......................................................................................................32
[Table 25. Test Patterns Register] ...............................................................................................................34
[Table 26. Image Windowing Register] .......................................................................................................35
[Table 27. Image Resolution Control]..........................................................................................................36
[Table 28. Mirror & Flip Register].................................................................................................................37
[Table 29. PLL Control Register] .................................................................................................................38
[Table 30. CSI Lane Mode Register]...........................................................................................................40
Rev 2.3/ Nov.2022
6
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