Datasheet > A6841SLWTR-T

A6841SLWTR-T

更新时间： 2024-02-15 01:10:04

品牌	Logo	应用领域
急速微 - ALLEGRO		驱动信息通信管理光电二极管接口集成电路
页数	文件大小	规格书
8页	328K
描述
SIPO Based Peripheral Driver, BICMOS, PDSO18, LEAD FREE, SOIC-18

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A6841SLWTR-T 技术参数

生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	18
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.82
其他特性：	SPLIT SUPPLY OPERATION POSSIBLE	内置保护：	TRANSIENT
接口集成电路类型：	SIPO BASED PERIPHERAL DRIVER	JESD-30 代码：	R-PDSO-G18
长度：	11.55 mm	功能数量：	1
端子数量：	18	最高工作温度：	85 °C
最低工作温度：	-20 °C	输出电流流向：	SINK
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
认证状态：	Not Qualified	座面最大高度：	2.65 mm
最大供电电压：	5.5 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	BICMOS	温度等级：	COMMERCIAL EXTENDED
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	7.5 mm
Base Number Matches：	1

A6841SLWTR-T 数据手册

A6841

DABiC-5 8-Bit Serial Input Latched Sink Drivers

Features and Benefits

▪ 3.3 to 5 V logic supply range

Description

The merging of low-power CMOS logic and bipolar output

power drivers using the proprietary DABiC-5 fabrication

process permit the A6841 integrated circuits to be used in a

wide variety of peripheral power driver applications. Each

device has an eight-bit CMOS shift register and CMOS

control circuitry, eight CMOS data latches, and eight bipolar

current-sinking Darlington output drivers. The 500 mA,

NPN Darlington outputs, with integral transient-suppression

diodes, are suitable for use with relays, solenoids, and other

inductive loads.

▪ Power-on reset (POR)

▪ To 10 MHz data input rate

▪ CMOS, TTL compatible inputs

▪ –40°C operation available

▪ Low-power CMOS logic and latches

▪ Schmitt trigger inputs for improved noise immunity

▪ High-voltage current-sink outputs

▪ Internal pull-up/pull-down resistors

▪ Output transient-protection diodes

▪ Single or split supply operation

AllpackagevariationsoftheA6841offerpremiumperformance

withaminimumoutput-breakdownvoltageratingof50V(35V

sustaining). All drivers can be operated with a split supply

where the negative supply is up to –20V.

Packages:

Not to scale

The CMOS inputs are compatible with standard CMOS logic

levels. TTLcircuits may require the use of appropriate pull-up

resistors.Byusingtheserialdataoutput,driverscanbecascaded

for interface applications requiring additional drive lines.

18-pin DIP (Package A)

The A6841 is provided in an 18-pin plastic DIP (suffix A), and

a 20-pin wide-body SOIC (suffix LW) with improved thermal

characteristicscomparedtothe18-pinSOICversionitreplaces

(100%pin-compatibleelectrically).Thesedevicesarelead(Pb)

free, with 100% matte tin plated leadframes.

20-pin SOICW (package LW)

(drop-in replacement for discon-

tinued 18-pin SOIC variants)

Applications include:

▪ Relays

▪ Solenoids

▪ Inductive loads

Functional Block Diagram

LOGIC

SUPPLY

CLOCK

SERIAL

DATA IN

SERIAL

DATA OUT

SERIAL-PARALLEL SHIFT REGISTER

LATCHES

STROBE

GROUND

OUTPUT ENABLE

(ACTIVE LOW)

MOS

BIPOLAR

VEE or POWER GROUND

SUB

OUT

OUT OUT

OUT

OUT OUT

OUT

26185.114F

12 3 4 5 6 7 8

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