A63P06361E-8F

更新时间： 2024-01-27 13:47:22

品牌	Logo	应用领域
联笙电子 - AMICC		计数器静态存储器
页数	文件大小	规格书
16页	280K
描述
1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output

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A63P06361E-8F 数据手册

A63P06361

Notes: 1. X = "Disregard", H = Logic High, L = Logic Low.

2. WRITE = L means:

1) Any BWx (BW1,BW2 ,BW3 , or BW4 ) and BWE are low or

2) GW is low.

3. All inputs except OE must be synchronized with setup and hold times around the rising edge (L-H) of CLK.

4. For write cycles that follow read cycles, OE must be HIGH before the input data request setup time and held

HIGH throughout the input data hold time.

5. ADSP LOW always initiates an internal Read at the L-H edge of CLK. A Write is performed by setting one or

more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. Refer to

the Write timing diagram for clarification.

Write Truth Table

Operation

BWE

BW1

BW2

BW3

BW4

READ

WRITE Byte 1

WRITE all bytes

PRELIMINARY (August, 2005, Version 0.0)

AMIC Technology, Corp.

1...4 5 678 9 10...16

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型号	品牌	描述	获取价格	数据表
A63P0636E	AMICC	1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output	获取价格
A63P0636E-2.6	AMICC	1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output	获取价格
A63P0636E-2.6F	AMICC	1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output	获取价格
A63P0636E-2.8	AMICC	1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output	获取价格
A63P0636E-2.8F	AMICC	1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output	获取价格
A63P0636E-3.2	AMICC	1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output	获取价格