A6279ELW-T

更新时间： 2024-02-29 02:16:39

品牌	Logo	应用领域
急速微 - ALLEGRO		显示驱动器驱动程序和接口接口集成电路光电二极管信息通信管理
页数	文件大小	规格书
18页	621K
描述
Serial-Input Constant-Current Latched LED Drivers with Open LED Detection

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技术参数
数据手册

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A6279ELW-T 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	SOP, SOP24,.4
针数：	24	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.82	Is Samacsys：	N
数据输入模式：	SERIAL	显示模式：	DOT MATRIX
接口集成电路类型：	LED DISPLAY DRIVER	JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e3	长度：	15.4 mm
湿度敏感等级：	3	复用显示功能：	NO
功能数量：	1	区段数：	16
端子数量：	24	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP24,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	电源：	3.3/5 V
认证状态：	Not Qualified	座面最大高度：	2.65 mm
子类别：	Display Drivers	最大供电电压：	5.5 V
最小供电电压：	3 V	标称供电电压：	5 V
表面贴装：	YES	技术：	BICMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	7.5 mm	Base Number Matches：	1

A6279ELW-T 数据手册

A6278 and

A6279

Serial-Input, Constant-Current Latched

LED Drivers with Open LED Detection

Functional Description

Open circuit detection does not take place until the sequence in

Normal Mode

Panel B on page 7 is performed. During this sequence, the OE

pin must be held low for a minimum of 2 μs (t_W(OE1)) to ensure

proper settling of the output currents and be given a minimum of

three CLOCK pulses. During the period that the OE pin is low

(active), OCD testing begins. The V_CEvoltage on each of the

output pins is compared to the Open LED Detection Theshold,

V_CE(OCD). If the V_CEof an enabled output is lower than V_CE(OCD)

an error bit value of 0 is set in the corresponding shift register. A

value of 1 will be set if no error is detected. If a particular output

is not enabled, a 0 will be set. The error codes are summarized in

the following table:

Serial data present at the SERIAL DATA IN input is transferred

to the shift register on the logic 0-to-logic 1 transition of the

CLOCK input pulse. On succeeding CLOCK pulses, the register

shifts data towards the SERIAL DATA OUT pin. The serial data

must appear at the input prior to the rising edge of the CLOCK

input waveform.

Data present in any register is transferred to the respective latch

when the LATCH ENABLE input is high (serial-to-parallel con-

version). The latches continue to accept new data as long as the

LATCH ENABLE input is held high.

Applications where the latches are bypassed (LATCH ENABLE

tied high) will require that the OUTPUT ENABLE input be high

during serial data entry. When the OUTPUT ENABLE input is

high, the output sink drivers are disabled (OFF).

Output State Test Condition Error Code Meaning

Output State

Test Condition Error Code

Meaning

N/A

OFF

N/A

_CE< V_CE(OCD)

Open/TSD

Normal

The data stored in the latches is not affected by the OUTPUT

ENABLE input. With the OUTPUT ENABLE input active (low),

the outputs are controlled by the state of their respective latches.

V_CE≥ V_CE(OCD)

LED Open Circuit Detection (Test) Mode

After the testing process, setting the OE pin high causes the shift

registers to latch the error code data where it can then be clocked

out of the SERIAL DATA OUT pin. The OCD latching sequence

(OE low, 3 CLOCK pulses, OE high as shown in panel B of the

LED OCD timing diagram) can then be repeated if necessary to

look for intermittent contact problems.

The LED Open Circuit Detection (OCD) mode, or Test mode,

is entered by clocking in the LED OCD mode initialization

sequence on the OUTPUT ENABLE (OE) and LATCH ENABLE

(LE) pins. In Normal mode, the OE and LE pins do not change

states while the CLOCK signal is cycling. The initialization

sequence is shown in panel A of the LED OCD timing require-

ments diagram on page 7.

The state of the outputs can be programmed with new data at any

time while in LED OCD mode (the same as in Normal mode).

This allows specific patterns to be tested for open circuits. The

pattern that is latched will then be tested during the OCD latching

sequence and the resulting bit values can be clocked out of the

SERIAL DATA OUT pin.

Note: Each step event during mode sequencing happens on the

leading edge of the CLOCK signal. Five step events (CLOCK

pulses) are required to enter OCD mode and five step events are

required to return to Normal mode.

A pattern, such as all highs, should first be loaded into the reg-

isters and latched leaving LE low. The device is then sequenced

into LED OCD mode. It should be noted that data is still being

sent through the shift registers while entering the LED OCD

mode. However, this data is not latched when the LE pin goes

high and sees a CLOCK pulse during the initialization sequence.

Note: LED Open Circuit Detection will not work properly if the

current is being externally limited by resistors to within the set

current limit for the device.

To return to Normal mode, perform the clocking sequence shown

in panel C of the timing diagram on the OE and LE pins.

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

1...4 5 678 9 10...18

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与A6279ELW-T相关器件

型号	品牌	描述	获取价格	数据表
A6279ELWTR-T	ALLEGRO	Serial-Input Constant-Current Latched LED Drivers with Open LED Detection	获取价格
A6280	ALLEGRO	3 Bit Constant Current LED Driver with PWM Control	获取价格
A6280_V	ALLEGRO	3-Channel Constant-Current LED Driver with Programmable PWM Control	获取价格
A6280EA-T	ALLEGRO	3 Bit Constant Current LED Driver with PWM Control	获取价格
A6280EES-T	ALLEGRO	LED Driver, 3-Segment, LEAD FREE, MO-220WEED-4, QFN-16	获取价格
A6280EESTR-T	ALLEGRO	3 Bit Constant Current LED Driver with PWM Control	获取价格

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