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A6259KA PDF预览

A6259KA

更新时间: 2024-01-12 21:21:15
品牌 Logo 应用领域
急速微 - ALLEGRO 外围驱动器驱动程序和接口接口集成电路光电二极管双倍数据速率
页数 文件大小 规格书
10页 173K
描述
8-BIT ADDRESSABLE DMOS POWER DRIVER

A6259KA 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.89内置保护:TRANSIENT
接口集成电路类型:SIPO BASED PERIPHERAL DRIVERJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:12.8 mm
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-40 °C
输出电流流向:SINK标称输出峰值电流:2 A
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240认证状态:Not Qualified
座面最大高度:2.65 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mmBase Number Matches:1

A6259KA 数据手册

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6259  
8-BIT ADDRESSABLE  
DMOS POWER DRIVER  
TERMINAL DESCRIPTIONS  
Terminal No.  
Terminal Name  
Function  
1
2
POWER GROUND  
Reference terminal for output voltage measurements (OUT0-3).  
(VDD) The logic supply voltage (typically 5 V).  
LOGIC SUPPLY  
3
S0  
OUT0  
Binary-coded output-select input, least-significant bit.  
Current-sinking, open-drain DMOS output, address 000.  
Current-sinking, open-drain DMOS output, address 001.  
Current-sinking, open-drain DMOS output, address 010.  
Current-sinking, open-drain DMOS output, address 011.  
Binary-coded output-select input.  
4
5
OUT1  
6
OUT2  
7
OUT3  
8
S1  
9
LOGIC GROUND  
POWER GROUND  
POWER GROUND  
S2  
Reference terminal for input voltage measurements.  
Reference terminal for output voltage measurements (OUT0-3).  
Reference terminal for output voltage measurements (OUT4-7).  
Binary-coded output-select input, most-significant bit.  
Mode control input; see Function Table.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
ENABLE  
OUT4  
Current-sinking, open-drain DMOS output, address 100.  
Current-sinking, open-drain DMOS output, address 101.  
Current-sinking, open-drain DMOS output, address 110.  
Current-sinking, open-drain DMOS output, address 111.  
OUT5  
OUT6  
OUT7  
DATA  
CMOS data input to the addressed output latch. When enabled, the  
addressed output inverts the data input (DATA = HIGH, OUTPUT = LOW).  
19  
20  
CLEAR  
Mode control input; see Function Table.  
POWER GROUND  
Reference terminal for output voltage measurements (OUT4-7).  
NOTE — Grounds (terminals 1, 9, 10, 11, and 20) must be connected externally to a single point.  
www.allegromicro.com  

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