A625308 Series
Preliminary
32K X 8 BIT CMOS SRAM
Features
nExternal Operating Voltage: 4.5V to 5.5V
nAccess times: 70 ns (max.)
nCurrent:
nFull static operation, no clock or refreshing required
nAll inputs and outputs are directly TTL compatible
nCommon I/O using three-state output
nData retention voltage: 2.0V (min.)
A625308-L series:
Operating: 70mA(max.)
nAvailable in 28-pin SOP and TSOP (forward and
reverse type) packages
Standby: 100mA(max.)
Operating: 70mA (max.)
Standby: 25mA (max.)
A625308-S series:
General Description
The A625308 is a low operating current 262,144-bit
static random access memory organized as 32,768
words by 8 bits and operates on a single 5V power
supply.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Minimum standby power is drawn by this device when
CE is at a high level, independent of the other input
levels.
Data retention is guaranteed at a power supply voltage
as low as 2.0V.
Pin Configurations
nSOP
nTSOP
1
VCC
WE
28
27
26
25
24
23
22
A14
A12
A7
OE
A11
A9
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
2
3
4
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A13
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A8
A6
A5
A4
A3
A9
5
6
A625308V
A11
9
OE
7
10
11
12
13
14
A2
A1
8
A10
CE
21
20
19
18
9
A1
A2
I/O7
10
11
A0
I/O0
I/O1
I/O2
I/O6
I/O5
I/O4
I/O3
12
13
14
17
16
15
A3
A4
A5
A6
A7
A12
A14
VCC
WE
A13
A8
A9
A11
OE
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A2
A1
A0
GND
I/O0
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A625308R
9
10
11
12
13
14
A10
PRELIMINARY
(December, 2000, Version 0.2)
1
AMIC Technology, Inc.