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A29DL324UV-120F PDF预览

A29DL324UV-120F

更新时间: 2024-01-11 15:42:27
品牌 Logo 应用领域
联笙电子 - AMICC 光电二极管内存集成电路闪存
页数 文件大小 规格书
57页 711K
描述
Flash, 2MX16, 120ns, PDSO48

A29DL324UV-120F 技术参数

是否Rohs认证: 符合生命周期:Contact Manufacturer
包装说明:TSSOP, TSSOP48,.8,20Reach Compliance Code:unknown
风险等级:5.69最长访问时间:120 ns
备用内存宽度:8启动块:BOTTOM
命令用户界面:YES通用闪存接口:YES
数据轮询:YESJESD-30 代码:R-PDSO-G48
内存密度:33554432 bit内存集成电路类型:FLASH
内存宽度:16部门数/规模:8,63
端子数量:48字数:2097152 words
字数代码:2000000最高工作温度:70 °C
最低工作温度:组织:2MX16
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP48,.8,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH并行/串行:PARALLEL
电源:3/3.3 V认证状态:Not Qualified
就绪/忙碌:YES部门规模:8K,64K
最大待机电流:0.000005 A子类别:Flash Memories
最大压摆率:0.045 mA表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL切换位:YES
类型:NOR TYPEBase Number Matches:1

A29DL324UV-120F 数据手册

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A29DL32x Series  
GENERAL DESCRIPTION  
A29DL32x Features  
The A29DL32x family consists of 32 megabit, 3.0 volt-only  
flash memory devices, organized as 2,097,152 words of 16  
bits each or 4,194,304 bytes of 8 bits each. Word mode data  
appears on I/O0–I/O15; byte mode data appears on I/O0–I/O7.  
The device is designed to be programmed in-system with the  
standard 3.0 volt VCC supply, and can also be programmed  
in standard EPROM programmers.  
The device offers complete compatibility with the JEDEC  
single-power-supply Flash command set standard.  
Commands are written to the command register using  
standard microprocessor write timings. Reading data out of  
the device is similar to reading from other Flash or EPROM  
devices.  
The device is available with an access time of 70, 80, 90, or  
120 ns. The devices are offered in 48-pin TSOP and 48-ball  
The host system can detect whether a program or erase  
operation is complete by using the device status bits:  
Fine-pitch TFBGA. Standard control pins—chip enable (  
),  
RY/  
pin, I/O7 (  
BY  
Polling) and I/O6/I/O2 (toggle bits).  
Data  
CE  
After a program or erase cycle has been completed, the  
device automatically returns to reading array data.  
The sector erase architecture allows memory sectors to be  
erased and reprogrammed without affecting the data  
contents of other sectors. The device is fully erased when  
shipped from the factory.  
Hardware data protection measures include a low VCC  
detector that automatically inhibits write operations during  
power transitions. The hardware sector protection feature  
disables both program and erase operations in any  
combination of the sectors of memory. This can be achieved  
write enable (  
), and output enable (  
OE  
)—control  
WE  
normal read and write operations, and avoid bus contention  
issues.  
The device requires only a single 3.0 volt power supply for  
both read and write functions. Internally generated and  
regulated voltages are provided for the program and erase  
operations.  
Simultaneous Read/Write Operations with Zero  
Latency  
The Simultaneous Read/Write architecture provides  
in-s y s t e m or via programming equipment.  
simultaneous operation by dividing the memory space into  
The device offers two power-saving features. When  
addresses have been stable for a specified amount of time,  
the device enters the automatic sleep mode. The system  
can also place the device into the standby mode. Power  
consumption is greatly reduced in both modes.  
two banks. The device can improve overall system  
performance by allowing a host system to program or erase  
in one bank, then immediately and simultaneously read from  
the other bank, with zero latency. This releases the system  
from waiting for the completion of program or erase  
operations.  
The A29DL32x devices use multiple bank architectures to  
provide flexibility for different applications. Three devices are  
available with these bank sizes:  
Device  
DL322  
DL323  
DL324  
Bank 1  
4 Mb  
Bank 2  
28 Mb  
24 Mb  
16 Mb  
8 Mb  
16 Mb  
(November, 2007, Version 1.2)  
2
AMIC Technology, Corp.  

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