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A29040BL-55F/Q

更新时间： 2024-01-06 03:58:13

品牌	Logo	应用领域
联笙电子 - AMICC		/
页数	文件大小	规格书
29页	388K
描述
Flash,

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技术参数
数据手册

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A29040BL-55F/Q 技术参数

是否Rohs认证：	符合	生命周期：	Contact Manufacturer
包装说明：	QCCJ,	Reach Compliance Code：	unknown
风险等级：	5.71	最长访问时间：	55 ns
JESD-30 代码：	R-PQCC-J32	长度：	13.97 mm
内存密度：	4194304 bit	内存集成电路类型：	FLASH
内存宽度：	8	功能数量：	1
端子数量：	32	字数：	524288 words
字数代码：	512000	工作模式：	ASYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	512KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	编程电压：	5 V
座面最大高度：	3.4 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	11.43 mm
Base Number Matches：	1

A29040BL-55F/Q 数据手册

A29040B Series

"Autoselect Mode" and "Autoselect Command Sequence"

sections for more information.

ICC2 in the Characteristics table represents the active current

specification for the write mode. The "AC Characteristics"

section contains timing specification tables and timing

diagrams for write operations.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive

the

and

pins to VIL.

is the power control and

selects the device.

data to the output pins.

is the output control and gates array

should remain at VIH all the time

during read operation. The internal state machine is set for

reading array data upon device power-up, or after a

hardware reset. This ensures that no spurious alteration of

the memory content occurs during the power transition. No

command is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid data

on the device data outputs. The device remains enabled for

read access until the command register contents are altered.

See "Reading Array Data" for more information. Refer to the

AC Read Operations table for timing specifications and to the

Read Operations Timings diagram for the timing waveforms,

l^CC1in the DC Characteristics table represents the active

current specification for reading array data.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status bits

on I/O7 - I/O0. Standard read cycle timings and ICC read

specifications apply. Refer to "Write Operation Status" for

more information, and to each AC Characteristics section for

timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it

can place the device in the standby mode. In this mode,

current consumption is greatly reduced, and the outputs are

placed in the high impedance state, independent of the

input.

Writing Commands/Command Sequences

The device enters the CMOS standby mode when the

pin is held at V^CC± 0.5V. (Note that this is a more restricted

voltage range than V^IH.) The device enters the TTL standby

To write a command or command sequence (which includes

programming data to the device and erasing sectors of

memory), the system must drive

and

to VIL, and

mode when

is held at VIH. The device requires the

to VIH. An erase operation can erase one sector,

standard access time (t^CE) before it is ready to read data.

If the device is deselected during erasure or programming,

the device draws active current until the operation is

completed.

I^CC3in the DC Characteristics tables represents the standby

current specification.

multiple sectors, or the entire device. The Sector Address

Tables indicate the address range that each sector occupies.

A "sector address" consists of the address inputs required to

uniquely select a sector. See the "Command Definitions"

section for details on erasing a sector or the entire chip, or

suspending/resuming the erase operation.

After the system writes the autoselect command sequence,

the device enters the autoselect mode. The system can then

read autoselect codes from the internal register (which is

separate from the memory array) on I/O⁷- I/O0. Standard

read cycle timings apply in this mode. Refer to the

Output Disable Mode

When the

input is at VIH, output from the device is

disabled. The output pins are placed in the high impedance

state.

Table 2. Sector Addresses Table

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

A18

A17

A16

Address Range

00000h - 0FFFFh

10000h - 1FFFFh

20000h - 2FFFFh

30000h - 3FFFFh

40000h - 4FFFFh

50000h - 5FFFFh

60000h - 6FFFFh

70000h - 7FFFFh

Note: All sectors are 64 Kbytes in size.

PRELIMINARY

(December, 2004, Version 0.2)

AMIC Technology, Corp.

1...3 4 567 8 9...29

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型号	品牌	描述	获取价格	数据表
A29040BL-55U	AMICC	512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory	获取价格
A29040BL-55UF	AMICC	512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory	获取价格
A29040BL-70	AMICC	512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory	获取价格
A29040BL-70F	AMICC	512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory	获取价格
A29040BL-70U	AMICC	512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory	获取价格
A29040BL-70UF	AMICC	512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory	获取价格

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