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A1440A-1VQG100I PDF预览

A1440A-1VQG100I

更新时间: 2024-01-09 02:12:39
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟可编程逻辑
页数 文件大小 规格书
90页 4430K
描述
Field Programmable Gate Array, 564 CLBs, 4000 Gates, 150MHz, CMOS, PQFP100, 1 MM HEIGHT, ROHS COMPLIANT, PLASTIC, VQFP-100

A1440A-1VQG100I 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:1 MM HEIGHT, MO-136, VQFP-100Reach Compliance Code:compliant
风险等级:5.78最大时钟频率:110 MHz
JESD-30 代码:S-PQFP-G100JESD-609代码:e3
长度:14 mm湿度敏感等级:3
可配置逻辑块数量:564等效关口数量:4000
端子数量:100最高工作温度:85 °C
最低工作温度:-40 °C组织:564 CLBS, 4000 GATES
封装主体材料:PLASTIC/EPOXY封装代码:TFQFP
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:1.2 mm
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:14 mm
Base Number Matches:1

A1440A-1VQG100I 数据手册

 浏览型号A1440A-1VQG100I的Datasheet PDF文件第4页浏览型号A1440A-1VQG100I的Datasheet PDF文件第5页浏览型号A1440A-1VQG100I的Datasheet PDF文件第6页浏览型号A1440A-1VQG100I的Datasheet PDF文件第8页浏览型号A1440A-1VQG100I的Datasheet PDF文件第9页浏览型号A1440A-1VQG100I的Datasheet PDF文件第10页 
1 – ACT 3 Family Overview  
General Description  
Microsemi’s ACT 3 Accelerator Series of FPGAs offers the industry’s fastest high-capacity  
programmable logic device. ACT 3 FPGAs offer a high performance, PCI compliant programmable  
solution capable of 186 MHz on-chip performance and 9.0 nanosecond clock-to-output (–1 speed grade),  
with capacities spanning from 1,500 to 10,000 gate array equivalent gates.  
The ACT 3 family builds on the proven two-module architecture consisting of combinatorial and  
sequential logic modules used in Microsemi’s 3200DX and 1200XL families. In addition, the ACT 3 I/O  
modules contain registers which deliver 9.0 nanosecond clock-to-out times (–1 speed grade). The  
devices contain four clock distribution networks, including dedicated array and I/O clocks, supporting  
very fast synchronous and asynchronous designs. In addition, routed clocks can be used to drive high  
fanout signals such as flip-flop resets and output.  
The ACT 3 family is supported by Microsemi’s Designer Series Development System which offers  
automatic placement and routing (with automatic or fixed pin assignments), static timing analysis, user  
programming, and debug and diagnostic probe capabilities.  
Accumulators (16-Bit)  
47 MHz  
Loadable Counters (16-Bit)  
82 MHz  
Prescaled Loadable Counters (16-Bit)  
Shift Registers  
186 MHz  
186 MHz  
Figure 1-1 • Predictable Performance (worst-case commercial, –1 speed grade)  
System Performance Model  
Chip #1 I/O Module  
Chip #2 I/O Module  
35 pF  
I/O CLK  
I/O CLK  
tCKHS  
tTRACE  
tINSU  
Revision 3  
1-1  
 
 

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