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A1425A-PLG84C PDF预览

A1425A-PLG84C

更新时间: 2024-02-19 03:07:13
品牌 Logo 应用领域
ACTEL 时钟可编程逻辑
页数 文件大小 规格书
68页 489K
描述
Field Programmable Gate Array, 310 CLBs, 2500 Gates, 125MHz, 310-Cell, CMOS, PQCC84, PLASTIC, LCC-84

A1425A-PLG84C 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:PLASTIC, LCC-84Reach Compliance Code:compliant
风险等级:5.77其他特性:MAX 70 I/OS
最大时钟频率:125 MHzCLB-Max的组合延迟:3 ns
JESD-30 代码:S-PQCC-J84JESD-609代码:e3
长度:29.3116 mm湿度敏感等级:3
可配置逻辑块数量:310等效关口数量:2500
输入次数:70逻辑单元数量:310
输出次数:70端子数量:84
最高工作温度:70 °C最低工作温度:
组织:310 CLBS, 2500 GATES封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC84,1.2SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):245电源:5 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Field Programmable Gate Arrays
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:29.3116 mm
Base Number Matches:1

A1425A-PLG84C 数据手册

 浏览型号A1425A-PLG84C的Datasheet PDF文件第2页浏览型号A1425A-PLG84C的Datasheet PDF文件第3页浏览型号A1425A-PLG84C的Datasheet PDF文件第4页浏览型号A1425A-PLG84C的Datasheet PDF文件第5页浏览型号A1425A-PLG84C的Datasheet PDF文件第6页浏览型号A1425A-PLG84C的Datasheet PDF文件第7页 
Accelerator Series FPGAs  
ACT3 Family  
F e a t u r e s  
Replaces up to twenty 32 macro-cell CPLDs  
Replaces up to one hundred 20-pin PAL® Packages  
Up to 1153 Dedicated Flip-Flops  
Up to 10,000 Gate Array Equivalent Gates  
(up to 25,000 equivalent PLD Gates)  
Highly Predictable Performance with 100% Automatic  
Placement and Routing  
VQFP, TQFP, BGA, and PQFP Packages  
Nonvolatile, User Programmable  
• 7.5 ns Clock-to-Output Times  
• Fully Tested Prior to Shipment  
Up to 250 MHz On-Chip Performance  
Up to 228 User-Programmable I/O Pins  
• Four Fast, Low-Skew Clock Networks  
More than 500 Macro Functions  
• 5.0V and 3.3V Versions  
Optimized for Logic Synthesis Methodologies  
Low-power CMOS Technology  
Device  
A1415  
A1425  
A1440  
A1460  
A14100  
Capacity  
Gate Array Equivalent Gates  
PLD Equivalent Gates  
TTL Equivalent Packages (40 gates)  
20-Pin PAL Equivalent Packages (100 gates)  
1,500  
3,750  
40  
2,500  
6,250  
60  
4,000  
10,000  
100  
6,000  
15,000  
150  
10,000  
25,000  
250  
15  
25  
40  
60  
100  
Logic Modules  
S-Module  
C-Module  
200  
104  
96  
310  
160  
150  
564  
288  
276  
848  
432  
416  
1,377  
697  
680  
1
Dedicated Flip-Flops  
264  
80  
360  
100  
568  
140  
768  
168  
1,153  
228  
User I/Os (maximum)  
2
Packages (by pin count)  
CPGA  
PLCC  
PQFP  
RQFP  
VQFP  
TQFP  
BGA  
100  
84  
100  
100  
133  
84  
100, 160  
175  
84  
160  
100  
176  
207  
160, 208  
257  
208  
100  
132  
176  
225  
196  
313  
256  
CQFP  
3
Performance (maximum, worst-case commercial)  
4
Chip-to-Chip  
108 MHz  
63 MHz  
110 MHz  
250 MHz  
250 MHz  
7.5 ns  
108 MHz  
63 MHz  
110 MHz  
250 MHz  
250 MHz  
7.5 ns  
100 MHz  
63 MHz  
110 MHz  
250 MHz  
250 MHz  
8.5 ns  
97 MHz  
63 MHz  
110 MHz  
200 MHz  
200 MHz  
9.0 ns  
93 MHz  
63 MHz  
105 MHz  
200 MHz  
200 MHz  
9.5 ns  
Accumulators (16-bit)  
Loadable Counter (16-bit)  
Prescaled Loadable Counters (16-bit)  
Datapath, Shift Registers  
Clock-to-Output (pad-to-pad)  
Notes:  
1. One flip-flop per S-Module, two flip-flops per I/O-Module.  
2. See product plan on page 1-178 for package availability.  
3. Based on A1415A-3, A1425A-3, A1440B-3, A1460B-3, and A14100B-3.  
4. Clock-to-Output + Setup  
S e p t e m b e r 1 9 9 7  
1 -1 7 5  
© 1997 Actel Corporation  

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