HiRel FPGAs
ACT 3 Description
unique architecture offers gate array flexibility, high
performance, and quick turnaround through user
programming. Device utilization is typically 95 percent of
available logic modules. All Actel devices include on-chip
clock drivers and a hard-wired distribution network.
The ACT 3 family is the third-generation Actel FPGA
family. This family offers the highest-performance and
highest-capacity devices, ranging from 2,500 to 10,000 gates,
with system performance up to 60 MHz over the military
temperature range. The devices have four clock distribution
networks, including dedicated array and I/O clocks. In
addition, the ACT 3 family offers the highest I/O-to-gate ratio
available. ACT 3 devices are manufactured using 0.8µ CMOS
technology.
User-definable I/Os are capable of driving at both TTL and
CMOS drive levels. Available packages for the military are the
Ceramic Quad Flat Pack (CQFP) and the Ceramic Pin Grid
Array (CPGA). See the “Product Plan” section on page 6 for
details.
QML Certification
1200XL/3200DX Description
Actel has achieved full QML certification, demonstrating
that quality management, procedures, processes, and
controls are in place and comply with MIL-PRF-38535, the
performance specification used by the Department of
Defense for monolithic integrated circuits. QML
certification is a good example of Actel's commitment to
supplying the highest quality products for all types of
high-reliability, military and space applications.
3200DX and 1200XL FPGAs were designed to integrate
system logic which is typically implemented in multiple
CPLDs, PALs, and FPGAs. These devices provide the features
and performance required for today’s complex, high-speed
digital logic systems. The 3200DX family offers the industry’s
fastest dual-port SRAM for implementing fast FIFOs, LIFOs,
and temporary data storage.
ACT 2 Description
Many suppliers of microelectronics components have
implemented QML as their primary worldwide business
system. Appropriate use of this system not only helps in the
implementation of advanced technologies, but also allows
for a quality, reliable and cost-effective logistics support
throughout QML products’ life cycles.
The ACT 2 family is the second-generation Actel FPGA family.
This family offers the best-value, high-capacity devices,
ranging from 4,000 to 8,000 gates, with system performance
up to 40 MHz over the military temperature range. The
devices have two routed array clock distribution networks.
ACT 2 devices are manufactured using 1.0µ CMOS technology.
Development Tool Support
ACT 1 Description
The HiRel devices are fully supported by Actel’s line of FPGA
development tools, including the Actel DeskTOP series and
Designer Advantage tools. The Actel DeskTOP Series is an
integrated design environment for PCs that includes design
entry, simulation, synthesis, and place and route tools.
Designer Advantage is Actel’s suite of FPGA development
point tools for PCs and Workstations that includes the
ACTgen Macro Builder, Designer with DirectTime timing
driven place and route and analysis tools, and device
programming software.
The ACT 1 family is the first Actel FPGA family and the first
antifuse-based FPGA. This family offers the lowest-cost logic
integration, with devices ranging from 1,200 to 2,000 gates,
with system performance up to 20 MHz over the military
temperature range. The devices have one routed array clock
distribution network. ACT 1 devices are manufactured using
1.0µ CMOS technology.
In addition, the HiRel devices contain ActionProbe circuitry
that provides built-in access to every node in a design,
enabling 100 percent real-time observation and analysis of a
device’s internal logic nodes without design iteration. The
probe circuitry is accessed by Silicon Explorer, an easy to use
integrated verification and logic analysis tool that can sample
data at 100 MHz (asynchronous) or 66 MHz (synchronous).
Silicon Explorer attaches to a PC’s standard COM port,
turning the PC into a fully functional 18 channel logic
analyzer. Silicon Explorer allows designers to complete the
design verification process at their desks and reduces
verification time from several hours per cycle to a few
seconds.
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